Sun J. Lin

Array ( [id] => 10508271 [patent_doc_number] => 09236147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-12 [patent_title] => 'Threshold carrying for solid state storage' [patent_app_type] => utility [patent_app_number] => 14/493216 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5291 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14493216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11039621 [patent_doc_number] => 20160236576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'CONTACTLESS CHARGING SYSTEM, VEHICLE, AND POWER SUPPLY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/024949 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8280 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15024949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12192272 [patent_doc_number] => 09895990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Method for programming energy flow between a grid and an accumulator of an electric vehicle, and corresponding device for programming' [patent_app_type] => utility [patent_app_number] => 14/914853 [patent_app_country] => US [patent_app_date] => 2014-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7095 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 445 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14914853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11202847 [patent_doc_number] => 09433081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-30 [patent_title] => 'Differential signal crosstalk minimization for dual stripline' [patent_app_type] => utility [patent_app_number] => 14/464129 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4523 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10507796 [patent_doc_number] => 09235671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-12 [patent_title] => 'Combining logic elements into pairs in a circuit design system' [patent_app_type] => utility [patent_app_number] => 14/460309 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10151047 [patent_doc_number] => 09183337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-10 [patent_title] => 'Circuit design with predefined configuration of parameterized cores' [patent_app_type] => utility [patent_app_number] => 14/455029 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9912428 [patent_doc_number] => 20150067630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/454539 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 16973 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11220799 [patent_doc_number] => 09449138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Prototype and emulation system for multiple custom prototype boards' [patent_app_type] => utility [patent_app_number] => 14/452368 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15600 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10930113 [patent_doc_number] => 20140333134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'POWER MANAGERS FOR AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/324297 [patent_app_country] => US [patent_app_date] => 2014-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7856 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14324297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10151043 [patent_doc_number] => 09183334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-10 [patent_title] => 'Verification of connectivity of signals in a circuit design' [patent_app_type] => utility [patent_app_number] => 14/323829 [patent_app_country] => US [patent_app_date] => 2014-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14323829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11014724 [patent_doc_number] => 20160211677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'METHOD AND PROGRAM FOR CONTROLLING POWER STORAGE SYSTEM AND STORAGE BATTERY' [patent_app_type] => utility [patent_app_number] => 14/915119 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7115 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14915119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10485931 [patent_doc_number] => 20150370950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'ARRAY WITH INTERCELL CONDUCTORS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS' [patent_app_type] => utility [patent_app_number] => 14/312285 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 22359 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14312285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10485930 [patent_doc_number] => 20150370949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'NANOWIRE OR 2D MATERIAL STRIPS INTERCONNECTS IN AN INTEGRATED CIRCUIT CELL' [patent_app_type] => utility [patent_app_number] => 14/312186 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 22355 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14312186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11233614 [patent_doc_number] => 09460846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Methods for forming shield materials onto inductive coils' [patent_app_type] => utility [patent_app_number] => 14/310694 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6125 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10303325 [patent_doc_number] => 20150188326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'BATTERY PACK, ELECTRONIC APPARATUS INCLUDING THE SAME, AND METHOD OF CONTROLLING CHARGE' [patent_app_type] => utility [patent_app_number] => 14/310214 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11208413 [patent_doc_number] => 09438048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Modular battery cell architecture and control method' [patent_app_type] => utility [patent_app_number] => 14/310506 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11259855 [patent_doc_number] => 09484765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Charging device and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/309791 [patent_app_country] => US [patent_app_date] => 2014-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16019 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14309791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11021577 [patent_doc_number] => 20160218532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'CIRCUIT PROTECTION METHOD AND APPARATUS, CHARGING DEVICE AND COMPUTER STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/024913 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4356 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15024913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10478515 [patent_doc_number] => 20150363532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'OPTIMIZATION OF INTEGRATED CIRCUITS FOR A RETICLE TRANSMISSION PROCESS WINDOW USING MULTIPLE FILL CELLS' [patent_app_type] => utility [patent_app_number] => 14/303764 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14303764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10556421 [patent_doc_number] => 09280622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Circuit verifying apparatus, circuit verifying method, and circuit verifying program' [patent_app_type] => utility [patent_app_number] => 14/301499 [patent_app_country] => US [patent_app_date] => 2014-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4855 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301499 [rel_patent_id] =>[rel_patent_doc_number] =>)