Search

Sun J. Lin

Examiner (ID: 2600, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9145854 [patent_doc_number] => 20130300377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'BATTERY STATE-OF-CHARGE ESTIMATOR USING ROBUST H(INFINITY) OBSERVER' [patent_app_type] => utility [patent_app_number] => 13/466374 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4158 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466374 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/466374
Battery state-of-charge estimator using robust H∞ observer May 7, 2012 Issued
Array ( [id] => 8588870 [patent_doc_number] => 20130007691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'MATCHING SYSTEMS WITH POWER AND THERMAL DOMAINS' [patent_app_type] => utility [patent_app_number] => 13/459863 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8043 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459863 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/459863
Matching systems with power and thermal domains Apr 29, 2012 Issued
Array ( [id] => 9156922 [patent_doc_number] => 08589837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-19 [patent_title] => 'Constructing inductive counterexamples in a multi-algorithm verification framework' [patent_app_type] => utility [patent_app_number] => 13/455839 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455839
Constructing inductive counterexamples in a multi-algorithm verification framework Apr 24, 2012 Issued
Array ( [id] => 9360897 [patent_doc_number] => 20140070769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'BRUSHLESS MOTOR CONTROL APPARATUS AND BRUSHLESS MOTOR CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/113507 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16668 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14113507 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/113507
Brushless motor control apparatus and brushless motor control method Apr 24, 2012 Issued
Array ( [id] => 8959174 [patent_doc_number] => 08504968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method to determine high level power distribution and interface problems in complex integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/451530 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9001 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451530 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/451530
Method to determine high level power distribution and interface problems in complex integrated circuits Apr 18, 2012 Issued
Array ( [id] => 8333275 [patent_doc_number] => 20120199979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'METHOD OF PROCESSING DUMMY PATTERN BASED ON BOUNDARY LENGTH AND DENSITY OF WIRING PATTERN, SEMICONDUCTOR DESIGN APPARATUS AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/450317 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7860 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450317 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450317
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device Apr 17, 2012 Issued
Array ( [id] => 9472553 [patent_doc_number] => 08726202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Mitigation of mask defects by pattern shifting' [patent_app_type] => utility [patent_app_number] => 13/446369 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 17316 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/446369
Mitigation of mask defects by pattern shifting Apr 12, 2012 Issued
Array ( [id] => 10009750 [patent_doc_number] => 09053272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Method and apparatus of hardware acceleration of EDA tools for a programmable logic device' [patent_app_type] => utility [patent_app_number] => 13/420002 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12080 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420002 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/420002
Method and apparatus of hardware acceleration of EDA tools for a programmable logic device Mar 13, 2012 Issued
Array ( [id] => 9049409 [patent_doc_number] => 08543967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Computer system and method for determining a temperature rise in direct current (DC) lines caused by joule heating of nearby alternating current (AC) lines' [patent_app_type] => utility [patent_app_number] => 13/405059 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6905 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405059 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405059
Computer system and method for determining a temperature rise in direct current (DC) lines caused by joule heating of nearby alternating current (AC) lines Feb 23, 2012 Issued
Array ( [id] => 8372602 [patent_doc_number] => 20120221988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/404629 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 15984 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404629 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404629
Method and system for power delivery network analysis Feb 23, 2012 Issued
Array ( [id] => 8959163 [patent_doc_number] => 08504957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Automated identification of power and ground nets in an integrated circuit netlist' [patent_app_type] => utility [patent_app_number] => 13/401704 [patent_app_country] => US [patent_app_date] => 2012-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13532 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13401704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/401704
Automated identification of power and ground nets in an integrated circuit netlist Feb 20, 2012 Issued
Array ( [id] => 9278290 [patent_doc_number] => 20140028258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'SNAP-FIT SEPARABLE MOBILE BACKUP POWER SUPPLY' [patent_app_type] => utility [patent_app_number] => 13/994983 [patent_app_country] => US [patent_app_date] => 2012-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2013 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994983 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994983
Snap-fit separable mobile backup power supply Feb 19, 2012 Issued
Array ( [id] => 9195717 [patent_doc_number] => 20130335032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'Charging Control System, Charging Control Method, and Recording Medium' [patent_app_type] => utility [patent_app_number] => 14/002678 [patent_app_country] => US [patent_app_date] => 2012-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7178 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14002678 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/002678
Charging control system, charging control method, and recording medium Feb 12, 2012 Issued
Array ( [id] => 8998279 [patent_doc_number] => 08522185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method for placement and routing of a circuit design' [patent_app_type] => utility [patent_app_number] => 13/366839 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366839
Method for placement and routing of a circuit design Feb 5, 2012 Issued
Array ( [id] => 8998279 [patent_doc_number] => 08522185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method for placement and routing of a circuit design' [patent_app_type] => utility [patent_app_number] => 13/366839 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366839
Method for placement and routing of a circuit design Feb 5, 2012 Issued
Array ( [id] => 8361014 [patent_doc_number] => 20120216168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'GATE CONFIGURATION DETERMINATION AND SELECTION FROM STANDARD CELL LIBRARY' [patent_app_type] => utility [patent_app_number] => 13/365989 [patent_app_country] => US [patent_app_date] => 2012-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13365989 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/365989
Gate configuration determination and selection from standard cell library Feb 2, 2012 Issued
Array ( [id] => 8952931 [patent_doc_number] => 20130198712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'Canonical Signature Generation For Layout Design Data' [patent_app_type] => utility [patent_app_number] => 13/364299 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7930 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364299 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364299
Canonical signature generation for layout design data Jan 31, 2012 Issued
Array ( [id] => 8912513 [patent_doc_number] => 08484590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Method of predicting electronic circuit floating gates' [patent_app_type] => utility [patent_app_number] => 13/345721 [patent_app_country] => US [patent_app_date] => 2012-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16619 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13345721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/345721
Method of predicting electronic circuit floating gates Jan 7, 2012 Issued
Array ( [id] => 8561936 [patent_doc_number] => 08336007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-18 [patent_title] => 'Verifiable multimode multipliers' [patent_app_type] => utility [patent_app_number] => 13/343898 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 8683 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13343898 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343898
Verifiable multimode multipliers Jan 4, 2012 Issued
Array ( [id] => 8985274 [patent_doc_number] => 08516404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processes' [patent_app_type] => utility [patent_app_number] => 13/341849 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12203 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13341849 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/341849
Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processes Dec 29, 2011 Issued
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