Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8810451 [patent_doc_number] => 08448118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Determining intra-die wirebond pad placement locations in integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/032059 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13032059 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/032059
Determining intra-die wirebond pad placement locations in integrated circuit Feb 21, 2011 Issued
Array ( [id] => 6042281 [patent_doc_number] => 20110204358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGN METHOD, DESIGN APPARATUS, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/032379 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5891 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20110204358.pdf [firstpage_image] =>[orig_patent_app_number] => 13032379 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/032379
Semiconductor integrated circuit device, design method, design apparatus, and program Feb 21, 2011 Issued
Array ( [id] => 8349365 [patent_doc_number] => 20120210284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'Method and Apparatus for Characterizing and Reducing Proximity Effect on Cell Electrical Characteristics' [patent_app_type] => utility [patent_app_number] => 13/027359 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11643 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13027359 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/027359
Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics Feb 14, 2011 Issued
Array ( [id] => 8424782 [patent_doc_number] => 08281280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Method and apparatus for versatile controllability and observability in prototype system' [patent_app_type] => utility [patent_app_number] => 13/025809 [patent_app_country] => US [patent_app_date] => 2011-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4391 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13025809 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/025809
Method and apparatus for versatile controllability and observability in prototype system Feb 10, 2011 Issued
Array ( [id] => 8214294 [patent_doc_number] => 20120131527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'TARGETED PRODUCTION CONTROL USING MULTIVARIATE ANALYSIS OF DESIGN MARGINALITIES' [patent_app_type] => utility [patent_app_number] => 13/023049 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131527.pdf [firstpage_image] =>[orig_patent_app_number] => 13023049 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/023049
Targeted production control using multivariate analysis of design marginalities Feb 7, 2011 Issued
Array ( [id] => 6189643 [patent_doc_number] => 20110126164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM TRANSFORMATION APPARATUS, AND MAPPING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/020409 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12025 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20110126164.pdf [firstpage_image] =>[orig_patent_app_number] => 13020409 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020409
SEMICONDUCTOR INTEGRATED CIRCUIT, PROGRAM TRANSFORMATION APPARATUS, AND MAPPING APPARATUS Feb 2, 2011 Abandoned
Array ( [id] => 8752257 [patent_doc_number] => 08418101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-09 [patent_title] => 'Temporal decomposition for design and verification' [patent_app_type] => utility [patent_app_number] => 13/020491 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 14648 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13020491 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020491
Temporal decomposition for design and verification Feb 2, 2011 Issued
Array ( [id] => 8741304 [patent_doc_number] => 08413090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-02 [patent_title] => 'Temporal decomposition for design and verification' [patent_app_type] => utility [patent_app_number] => 13/020476 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 14683 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13020476 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020476
Temporal decomposition for design and verification Feb 2, 2011 Issued
Array ( [id] => 8985281 [patent_doc_number] => 08516411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Register transfer level design compilation advisor' [patent_app_type] => utility [patent_app_number] => 13/017929 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8275 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13017929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017929
Register transfer level design compilation advisor Jan 30, 2011 Issued
Array ( [id] => 9029808 [patent_doc_number] => 08539406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Equivalence checking for retimed electronic circuit designs' [patent_app_type] => utility [patent_app_number] => 13/018229 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6685 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018229
Equivalence checking for retimed electronic circuit designs Jan 30, 2011 Issued
Array ( [id] => 8946073 [patent_doc_number] => 08499260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Optical proximity correction verification accounting for mask deviations' [patent_app_type] => utility [patent_app_number] => 13/014159 [patent_app_country] => US [patent_app_date] => 2011-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13014159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/014159
Optical proximity correction verification accounting for mask deviations Jan 25, 2011 Issued
Array ( [id] => 8610506 [patent_doc_number] => 20130015818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'CIRCUIT ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 13/578263 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3231 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13578263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/578263
CIRCUIT ASSEMBLY Jan 18, 2011 Abandoned
Array ( [id] => 8693332 [patent_doc_number] => 08392867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists' [patent_app_type] => utility [patent_app_number] => 13/005599 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10022 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13005599 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/005599
System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists Jan 12, 2011 Issued
Array ( [id] => 6171160 [patent_doc_number] => 20110175658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING VOLTAGE CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 13/005289 [patent_app_country] => US [patent_app_date] => 2011-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11850 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175658.pdf [firstpage_image] =>[orig_patent_app_number] => 13005289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/005289
Semiconductor integrated circuit and operating voltage control method Jan 11, 2011 Issued
Array ( [id] => 8678850 [patent_doc_number] => 08386986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Temperature controlled attenuator' [patent_app_type] => utility [patent_app_number] => 12/978179 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 36465 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978179 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/978179
Temperature controlled attenuator Dec 22, 2010 Issued
Array ( [id] => 8728510 [patent_doc_number] => 08407652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Task-based multi-process design synthesis' [patent_app_type] => utility [patent_app_number] => 12/972879 [patent_app_country] => US [patent_app_date] => 2010-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 14579 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12972879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/972879
Task-based multi-process design synthesis Dec 19, 2010 Issued
Array ( [id] => 8230154 [patent_doc_number] => 20120144358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs' [patent_app_type] => utility [patent_app_number] => 12/959029 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10479 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12959029 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/959029
Resolving global coupling timing and slew violations for buffer-dominated designs Dec 1, 2010 Issued
Array ( [id] => 8424775 [patent_doc_number] => 08281273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/957389 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 10040 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12957389 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/957389
Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Nov 29, 2010 Issued
Array ( [id] => 8849422 [patent_doc_number] => 08458622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Photo-mask acceptance technique' [patent_app_type] => utility [patent_app_number] => 12/955569 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12955569 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/955569
Photo-mask acceptance technique Nov 28, 2010 Issued
Array ( [id] => 8728513 [patent_doc_number] => 08407655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Fixing design requirement violations in multiple multi-corner multi-mode scenarios' [patent_app_type] => utility [patent_app_number] => 12/949689 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12949689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/949689
Fixing design requirement violations in multiple multi-corner multi-mode scenarios Nov 17, 2010 Issued
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