Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9102872 [patent_doc_number] => 08566766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method for detecting small delay defects' [patent_app_type] => utility [patent_app_number] => 12/943379 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2499 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943379
Method for detecting small delay defects Nov 9, 2010 Issued
Array ( [id] => 8623346 [patent_doc_number] => 08356267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Statistical method for hierarchically routing layout utilizing flat route information' [patent_app_type] => utility [patent_app_number] => 12/912819 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5499 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12912819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/912819
Statistical method for hierarchically routing layout utilizing flat route information Oct 26, 2010 Issued
Array ( [id] => 8060137 [patent_doc_number] => 20110246954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD AND APPARATUS FOR ANALYZING FAULT BEHAVIOR' [patent_app_type] => utility [patent_app_number] => 12/912429 [patent_app_country] => US [patent_app_date] => 2010-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246954.pdf [firstpage_image] =>[orig_patent_app_number] => 12912429 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/912429
Method and apparatus for analyzing fault behavior of a software design model Oct 25, 2010 Issued
Array ( [id] => 8552407 [patent_doc_number] => 08327306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Method for optimizing location and number of power/ground pads on power/ground distribution network with multiple voltage domains' [patent_app_type] => utility [patent_app_number] => 12/911789 [patent_app_country] => US [patent_app_date] => 2010-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5888 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12911789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/911789
Method for optimizing location and number of power/ground pads on power/ground distribution network with multiple voltage domains Oct 25, 2010 Issued
Array ( [id] => 8366785 [patent_doc_number] => 08255861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Efficient replaying of autograded coverage regressions and performance verification with directed testcases' [patent_app_type] => utility [patent_app_number] => 12/909562 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 17730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12909562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/909562
Efficient replaying of autograded coverage regressions and performance verification with directed testcases Oct 20, 2010 Issued
Array ( [id] => 8574901 [patent_doc_number] => 08341564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Method and system for optimizing migrated implementation of a system design' [patent_app_type] => utility [patent_app_number] => 12/909209 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8504 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12909209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/909209
Method and system for optimizing migrated implementation of a system design Oct 20, 2010 Issued
Array ( [id] => 8403562 [patent_doc_number] => 20120235625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'ENERGY STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/500387 [patent_app_country] => US [patent_app_date] => 2010-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12364 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13500387 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/500387
Energy storage system Sep 30, 2010 Issued
Array ( [id] => 8412690 [patent_doc_number] => 08276103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Photomask designing method, photomask manufacturing method, and photomask designing program' [patent_app_type] => utility [patent_app_number] => 12/883299 [patent_app_country] => US [patent_app_date] => 2010-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 6093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12883299 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/883299
Photomask designing method, photomask manufacturing method, and photomask designing program Sep 15, 2010 Issued
Array ( [id] => 8389150 [patent_doc_number] => 08266562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Method and system for configurable contacts for implementing different bias designs of an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/880760 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12880760 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/880760
Method and system for configurable contacts for implementing different bias designs of an integrated circuit device Sep 12, 2010 Issued
Array ( [id] => 6204202 [patent_doc_number] => 20110066988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Method, System, Computer Program Product, and Data Processing Program for Verification of Logic Circuit Designs Using Dynamic Clock Gating' [patent_app_type] => utility [patent_app_number] => 12/876319 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4532 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066988.pdf [firstpage_image] =>[orig_patent_app_number] => 12876319 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876319
Verification of logic circuit designs using dynamic clock gating Sep 6, 2010 Issued
Array ( [id] => 7809179 [patent_doc_number] => 20120060133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'Annotation of RTL to Simplify Timing Analysis' [patent_app_type] => utility [patent_app_number] => 12/876659 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5291 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20120060133.pdf [firstpage_image] =>[orig_patent_app_number] => 12876659 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876659
Annotation of RTL to Simplify Timing Analysis Sep 6, 2010 Abandoned
Array ( [id] => 8183364 [patent_doc_number] => 08181142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/923137 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 7835 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181142.pdf [firstpage_image] =>[orig_patent_app_number] => 12923137 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923137
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device Sep 2, 2010 Issued
Array ( [id] => 6032150 [patent_doc_number] => 20110055782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'PROXIMITY-AWARE CIRCUIT DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/870559 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055782.pdf [firstpage_image] =>[orig_patent_app_number] => 12870559 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/870559
Method and system for proximity-aware circuit design Aug 26, 2010 Issued
Array ( [id] => 8451179 [patent_doc_number] => 20120262125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'METHOD AND CHARGE CONTROL FOR PROLONGING THE USEFUL LIFE OF BATTERIES' [patent_app_type] => utility [patent_app_number] => 13/500124 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6108 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13500124 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/500124
METHOD AND CHARGE CONTROL FOR PROLONGING THE USEFUL LIFE OF BATTERIES Aug 25, 2010 Abandoned
Array ( [id] => 8319820 [patent_doc_number] => 08234612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Cone-aware spare cell placement using hypergraph connectivity analysis' [patent_app_type] => utility [patent_app_number] => 12/862949 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5627 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12862949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/862949
Cone-aware spare cell placement using hypergraph connectivity analysis Aug 24, 2010 Issued
Array ( [id] => 7780739 [patent_doc_number] => 20120042295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'AUTOMATED PLANNING IN PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/855009 [patent_app_country] => US [patent_app_date] => 2010-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042295.pdf [firstpage_image] =>[orig_patent_app_number] => 12855009 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/855009
Automated planning in physical synthesis Aug 11, 2010 Issued
Array ( [id] => 6198185 [patent_doc_number] => 20110029943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/834339 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20110029943.pdf [firstpage_image] =>[orig_patent_app_number] => 12834339 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834339
Method for manufacturing semiconductor integrated circuit and recording medium Jul 11, 2010 Issued
Array ( [id] => 8285832 [patent_doc_number] => 08219949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Nonsequential hardware design synthesis verification' [patent_app_type] => utility [patent_app_number] => 12/821109 [patent_app_country] => US [patent_app_date] => 2010-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4616 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12821109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/821109
Nonsequential hardware design synthesis verification Jun 21, 2010 Issued
Array ( [id] => 8472870 [patent_doc_number] => 08302063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression' [patent_app_type] => utility [patent_app_number] => 12/782359 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12782359 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782359
Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression May 17, 2010 Issued
Array ( [id] => 6258553 [patent_doc_number] => 20100296069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'Pattern division method, pattern division processing apparatus and information storage medium on which is stored a program' [patent_app_type] => utility [patent_app_number] => 12/662959 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8688 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20100296069.pdf [firstpage_image] =>[orig_patent_app_number] => 12662959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662959
Pattern division method, pattern division processing apparatus and information storage medium on which is stored a program May 12, 2010 Abandoned
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