Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8564155 [patent_doc_number] => 20120326726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'STATE-OF-CHARGE ESTIMATION APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/580625 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9178 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580625 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/580625
State-of-charge estimation apparatus Mar 25, 2010 Issued
Array ( [id] => 9257970 [patent_doc_number] => 08621413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-31 [patent_title] => 'System, method, and computer program product for reducing a deactivation function utilizing an optimal reduction' [patent_app_type] => utility [patent_app_number] => 12/723539 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9206 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12723539 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723539
System, method, and computer program product for reducing a deactivation function utilizing an optimal reduction Mar 11, 2010 Issued
Array ( [id] => 8297465 [patent_doc_number] => 08225267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Method and apparatus for analyzing structure of complex material layer, and storage medium storing program for causing a computer to execute thereof method' [patent_app_type] => utility [patent_app_number] => 12/659399 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5780 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12659399 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659399
Method and apparatus for analyzing structure of complex material layer, and storage medium storing program for causing a computer to execute thereof method Mar 7, 2010 Issued
Array ( [id] => 6400285 [patent_doc_number] => 20100148235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT, STANDARD CELL, STANDARD CELL LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING EQUIPMENT' [patent_app_type] => utility [patent_app_number] => 12/714819 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11710 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148235.pdf [firstpage_image] =>[orig_patent_app_number] => 12714819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714819
Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment Feb 28, 2010 Issued
Array ( [id] => 8552399 [patent_doc_number] => 08327298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'System and method for evaluating error sources associated with a mask' [patent_app_type] => utility [patent_app_number] => 12/713109 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 8707 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12713109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/713109
System and method for evaluating error sources associated with a mask Feb 24, 2010 Issued
Array ( [id] => 8514173 [patent_doc_number] => 20120313581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'VEHICLE' [patent_app_type] => utility [patent_app_number] => 13/580652 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6264 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580652 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/580652
Vehicle Feb 22, 2010 Issued
Array ( [id] => 6652440 [patent_doc_number] => 20100229139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/702129 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5680 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229139.pdf [firstpage_image] =>[orig_patent_app_number] => 12702129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702129
SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT Feb 7, 2010 Abandoned
Array ( [id] => 8033901 [patent_doc_number] => 08146048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'System and method for removing T-point elements with unused stubs from a PCB layout design' [patent_app_type] => utility [patent_app_number] => 12/699839 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1543 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146048.pdf [firstpage_image] =>[orig_patent_app_number] => 12699839 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699839
System and method for removing T-point elements with unused stubs from a PCB layout design Feb 2, 2010 Issued
Array ( [id] => 8297450 [patent_doc_number] => 08225251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Circuit states' [patent_app_type] => utility [patent_app_number] => 12/694199 [patent_app_country] => US [patent_app_date] => 2010-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12694199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/694199
Circuit states Jan 25, 2010 Issued
Array ( [id] => 8546524 [patent_doc_number] => 08321827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Power supply design' [patent_app_type] => utility [patent_app_number] => 12/693439 [patent_app_country] => US [patent_app_date] => 2010-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 11511 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12693439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/693439
Power supply design Jan 24, 2010 Issued
Array ( [id] => 8220436 [patent_doc_number] => 08196085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-05 [patent_title] => 'Interactive design optimization techniques and interface' [patent_app_type] => utility [patent_app_number] => 12/690059 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/196/08196085.pdf [firstpage_image] =>[orig_patent_app_number] => 12690059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690059
Interactive design optimization techniques and interface Jan 18, 2010 Issued
Array ( [id] => 8787180 [patent_doc_number] => 08434036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Arithmetic program conversion apparatus, arithmetic program conversion method, and program' [patent_app_type] => utility [patent_app_number] => 12/689579 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11014 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12689579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689579
Arithmetic program conversion apparatus, arithmetic program conversion method, and program Jan 18, 2010 Issued
Array ( [id] => 8546525 [patent_doc_number] => 08321828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance' [patent_app_type] => utility [patent_app_number] => 12/684819 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12684819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684819
Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance Jan 7, 2010 Issued
Array ( [id] => 6032151 [patent_doc_number] => 20110055783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'CODE TILING SCHEME FOR DEEP-SUBMICRON ROM COMPILERS' [patent_app_type] => utility [patent_app_number] => 12/683599 [patent_app_country] => US [patent_app_date] => 2010-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055783.pdf [firstpage_image] =>[orig_patent_app_number] => 12683599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/683599
Code tiling scheme for deep-submicron ROM compilers Jan 6, 2010 Issued
Array ( [id] => 8023015 [patent_doc_number] => 08141027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Automated sensitivity definition and calibration for design for manufacturing tools' [patent_app_type] => utility [patent_app_number] => 12/652409 [patent_app_country] => US [patent_app_date] => 2010-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4362 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141027.pdf [firstpage_image] =>[orig_patent_app_number] => 12652409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/652409
Automated sensitivity definition and calibration for design for manufacturing tools Jan 4, 2010 Issued
Array ( [id] => 8285833 [patent_doc_number] => 08219948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Layout verification device, layout verification program, and layout verification method of layout pattern of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/651739 [patent_app_country] => US [patent_app_date] => 2010-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8958 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12651739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651739
Layout verification device, layout verification program, and layout verification method of layout pattern of semiconductor device Jan 3, 2010 Issued
Array ( [id] => 6513041 [patent_doc_number] => 20100095254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SYSTEM AND METHOD FOR TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN' [patent_app_type] => utility [patent_app_number] => 12/631899 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6057 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20100095254.pdf [firstpage_image] =>[orig_patent_app_number] => 12631899 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631899
System and method for testing pattern sensitive algorithms for semiconductor design Dec 6, 2009 Issued
Array ( [id] => 8343237 [patent_doc_number] => 08245172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Methods and apparatus for defining Manhattan power grid structures having a reduced number of vias' [patent_app_type] => utility [patent_app_number] => 12/611116 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12611116 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/611116
Methods and apparatus for defining Manhattan power grid structures having a reduced number of vias Nov 1, 2009 Issued
Array ( [id] => 8924093 [patent_doc_number] => 08490042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Performing routing optimization during circuit design' [patent_app_type] => utility [patent_app_number] => 12/608434 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 11964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12608434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608434
Performing routing optimization during circuit design Oct 28, 2009 Issued
Array ( [id] => 8558306 [patent_doc_number] => 08332794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Circuits and methods for programmable transistor array' [patent_app_type] => utility [patent_app_number] => 12/605209 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7026 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12605209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605209
Circuits and methods for programmable transistor array Oct 22, 2009 Issued
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