Search

Sun J. Lin

Examiner (ID: 7433, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6492920 [patent_doc_number] => 20100042959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => ' Test pattern coverage through parallel discard, flow control, and quality metrics' [patent_app_type] => utility [patent_app_number] => 12/603406 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042959.pdf [firstpage_image] =>[orig_patent_app_number] => 12603406 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603406
Improving test pattern coverage through parallel discard, flow control, and quality metrics Oct 20, 2009 Issued
Array ( [id] => 7680891 [patent_doc_number] => 20100023917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'TOOL FOR MODIFYING MASK DESIGN LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/566925 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3195 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023917.pdf [firstpage_image] =>[orig_patent_app_number] => 12566925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566925
Tool for modifying mask design layout Sep 24, 2009 Issued
Array ( [id] => 6384646 [patent_doc_number] => 20100077271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Method of achieving convergence of hold time error, device and program therefor' [patent_app_type] => utility [patent_app_number] => 12/585629 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9542 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20100077271.pdf [firstpage_image] =>[orig_patent_app_number] => 12585629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585629
Method of achieving convergence of hold time error, device and program therefor Sep 20, 2009 Issued
Array ( [id] => 8247242 [patent_doc_number] => 08205183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-19 [patent_title] => 'Interactive configuration of connectivity in schematic diagram of integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/562889 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 7105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/205/08205183.pdf [firstpage_image] =>[orig_patent_app_number] => 12562889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562889
Interactive configuration of connectivity in schematic diagram of integrated circuit design Sep 17, 2009 Issued
Array ( [id] => 6204206 [patent_doc_number] => 20110066992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Hardware Description Language (HDL) Generation Systems and Methods For Custom Circuit Boards' [patent_app_type] => utility [patent_app_number] => 12/561329 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6740 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066992.pdf [firstpage_image] =>[orig_patent_app_number] => 12561329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561329
Hardware description language (HDL) generation systems and methods for custom circuit boards Sep 16, 2009 Issued
Array ( [id] => 8273259 [patent_doc_number] => 08214791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-03 [patent_title] => 'User interface for inherited connections in a circuit' [patent_app_type] => utility [patent_app_number] => 12/561999 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12561999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561999
User interface for inherited connections in a circuit Sep 16, 2009 Issued
Array ( [id] => 8149425 [patent_doc_number] => 08166445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'Estimating Icc current temperature scaling factor of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/558109 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166445.pdf [firstpage_image] =>[orig_patent_app_number] => 12558109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558109
Estimating Icc current temperature scaling factor of an integrated circuit Sep 10, 2009 Issued
Array ( [id] => 8171005 [patent_doc_number] => 08176453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Power-aware debugging' [patent_app_type] => utility [patent_app_number] => 12/558259 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 7211 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176453.pdf [firstpage_image] =>[orig_patent_app_number] => 12558259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558259
Power-aware debugging Sep 10, 2009 Issued
Array ( [id] => 6641269 [patent_doc_number] => 20100005439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'DESIGNING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/556649 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20100005439.pdf [firstpage_image] =>[orig_patent_app_number] => 12556649 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556649
Designing method of semiconductor integrated circuit Sep 9, 2009 Issued
Array ( [id] => 8149406 [patent_doc_number] => 08166423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Photomask design verification' [patent_app_type] => utility [patent_app_number] => 12/555219 [patent_app_country] => US [patent_app_date] => 2009-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166423.pdf [firstpage_image] =>[orig_patent_app_number] => 12555219 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555219
Photomask design verification Sep 7, 2009 Issued
Array ( [id] => 6032148 [patent_doc_number] => 20110055781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'NON-INVASIVE TIMING CHARACTERIZATION OF INTEGRATED CIRCUITS USING SENSITIZABLE SIGNAL PATHS AND SPARSE EQUATIONS' [patent_app_type] => utility [patent_app_number] => 12/550119 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14608 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055781.pdf [firstpage_image] =>[orig_patent_app_number] => 12550119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550119
Non-invasive timing characterization of integrated circuits using sensitizable signal paths and sparse equations Aug 27, 2009 Issued
Array ( [id] => 6596631 [patent_doc_number] => 20100062549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'PATTERN CORRECTING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND PATTERN CORRECTING PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/549209 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20100062549.pdf [firstpage_image] =>[orig_patent_app_number] => 12549209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549209
PATTERN CORRECTING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND PATTERN CORRECTING PROGRAM Aug 26, 2009 Abandoned
Array ( [id] => 8109617 [patent_doc_number] => 08156460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Method of estimating a leakage current in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/547729 [patent_app_country] => US [patent_app_date] => 2009-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 10022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156460.pdf [firstpage_image] =>[orig_patent_app_number] => 12547729 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/547729
Method of estimating a leakage current in a semiconductor device Aug 25, 2009 Issued
Array ( [id] => 5376034 [patent_doc_number] => 20090313595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS' [patent_app_type] => utility [patent_app_number] => 12/546959 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12566 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313595.pdf [firstpage_image] =>[orig_patent_app_number] => 12546959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546959
Stress-managed revision of integrated circuit layouts Aug 24, 2009 Issued
Array ( [id] => 5376030 [patent_doc_number] => 20090313591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'METHOD FOR GENERATING A DEEP N-WELL PATTERN FOR AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/544149 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313591.pdf [firstpage_image] =>[orig_patent_app_number] => 12544149 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/544149
Method for generating a deep N-well pattern for an integrated circuit design Aug 18, 2009 Issued
Array ( [id] => 5374052 [patent_doc_number] => 20090311613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'Mask for multi-column electron beam exposure, and electron beam exposure apparatus and exposure method using the same' [patent_app_type] => utility [patent_app_number] => 12/583319 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6833 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0311/20090311613.pdf [firstpage_image] =>[orig_patent_app_number] => 12583319 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583319
Mask for multi-column electron beam exposure, and electron beam exposure apparatus and exposure method using the same Aug 17, 2009 Issued
Array ( [id] => 8022989 [patent_doc_number] => 08141014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'System and method for common history pessimism relief during static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/538229 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7642 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141014.pdf [firstpage_image] =>[orig_patent_app_number] => 12538229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538229
System and method for common history pessimism relief during static timing analysis Aug 9, 2009 Issued
Array ( [id] => 8546513 [patent_doc_number] => 08321815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Recording medium storing original data generation program, original data generation method, original fabricating method, exposure method, and device manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/512649 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 11941 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12512649 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512649
Recording medium storing original data generation program, original data generation method, original fabricating method, exposure method, and device manufacturing method Jul 29, 2009 Issued
Array ( [id] => 6263452 [patent_doc_number] => 20100031213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'DESIGN INFORMATION GENERATING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/511549 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20100031213.pdf [firstpage_image] =>[orig_patent_app_number] => 12511549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511549
DESIGN INFORMATION GENERATING APPARATUS Jul 28, 2009 Abandoned
Array ( [id] => 6100652 [patent_doc_number] => 20110004857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'LOGIC DIFFERENCE SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/497499 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8038 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004857.pdf [firstpage_image] =>[orig_patent_app_number] => 12497499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497499
Logic difference synthesis Jul 1, 2009 Issued
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