Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9077620 [patent_doc_number] => 08555212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Manufacturability' [patent_app_type] => utility [patent_app_number] => 12/334369 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12334369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334369
Manufacturability Dec 11, 2008 Issued
Array ( [id] => 9077620 [patent_doc_number] => 08555212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Manufacturability' [patent_app_type] => utility [patent_app_number] => 12/334369 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12334369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334369
Manufacturability Dec 11, 2008 Issued
Array ( [id] => 9077620 [patent_doc_number] => 08555212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Manufacturability' [patent_app_type] => utility [patent_app_number] => 12/334369 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12334369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334369
Manufacturability Dec 11, 2008 Issued
Array ( [id] => 9077620 [patent_doc_number] => 08555212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Manufacturability' [patent_app_type] => utility [patent_app_number] => 12/334369 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12334369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334369
Manufacturability Dec 11, 2008 Issued
Array ( [id] => 4614404 [patent_doc_number] => 07996811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Power managers for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/332529 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7803 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996811.pdf [firstpage_image] =>[orig_patent_app_number] => 12332529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332529
Power managers for an integrated circuit Dec 10, 2008 Issued
Array ( [id] => 8171032 [patent_doc_number] => 08176458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Increased effective flip-flop density in a structured ASIC' [patent_app_type] => utility [patent_app_number] => 12/325629 [patent_app_country] => US [patent_app_date] => 2008-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8441 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176458.pdf [firstpage_image] =>[orig_patent_app_number] => 12325629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/325629
Increased effective flip-flop density in a structured ASIC Nov 30, 2008 Issued
Array ( [id] => 7706539 [patent_doc_number] => 08091058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Methods, computer-readable media and computer-implemented tools for pre-route repeater insertion' [patent_app_type] => utility [patent_app_number] => 12/324439 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 8618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091058.pdf [firstpage_image] =>[orig_patent_app_number] => 12324439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/324439
Methods, computer-readable media and computer-implemented tools for pre-route repeater insertion Nov 25, 2008 Issued
Array ( [id] => 5454692 [patent_doc_number] => 20090070729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'METHOD AND SOFTWARE TOOL FOR DESIGNING AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/267859 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4715 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070729.pdf [firstpage_image] =>[orig_patent_app_number] => 12267859 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/267859
Method and software tool for designing an integrated circuit Nov 9, 2008 Issued
Array ( [id] => 137353 [patent_doc_number] => 07698672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-13 [patent_title] => 'Methods of minimizing leakage current' [patent_app_type] => utility [patent_app_number] => 12/268344 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3029 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698672.pdf [firstpage_image] =>[orig_patent_app_number] => 12268344 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/268344
Methods of minimizing leakage current Nov 9, 2008 Issued
Array ( [id] => 7683918 [patent_doc_number] => 20100122223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'Techniques for Computing Capacitances in a Medium With Three-Dimensional Conformal Dielectrics' [patent_app_type] => utility [patent_app_number] => 12/267599 [patent_app_country] => US [patent_app_date] => 2008-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8040 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122223.pdf [firstpage_image] =>[orig_patent_app_number] => 12267599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/267599
Techniques for Computing Capacitances in a Medium With Three-Dimensional Conformal Dielectrics Nov 8, 2008 Abandoned
Array ( [id] => 7537756 [patent_doc_number] => 08051399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis' [patent_app_type] => utility [patent_app_number] => 12/265719 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8881 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051399.pdf [firstpage_image] =>[orig_patent_app_number] => 12265719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265719
IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis Nov 4, 2008 Issued
Array ( [id] => 5266937 [patent_doc_number] => 20090119622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols' [patent_app_type] => utility [patent_app_number] => 12/265549 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 22578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119622.pdf [firstpage_image] =>[orig_patent_app_number] => 12265549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265549
Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols Nov 4, 2008 Abandoned
Array ( [id] => 5339327 [patent_doc_number] => 20090055791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'PROCESS AND APPARATUS FOR ADJUSTING TRACES' [patent_app_type] => utility [patent_app_number] => 12/259779 [patent_app_country] => US [patent_app_date] => 2008-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9085 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055791.pdf [firstpage_image] =>[orig_patent_app_number] => 12259779 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/259779
Process and apparatus for adjusting traces Oct 27, 2008 Issued
Array ( [id] => 7734873 [patent_doc_number] => 08104000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method and apparatus for memory abstraction and for word level net list reduction and verification using same' [patent_app_type] => utility [patent_app_number] => 12/258759 [patent_app_country] => US [patent_app_date] => 2008-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 15172 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/104/08104000.pdf [firstpage_image] =>[orig_patent_app_number] => 12258759 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/258759
Method and apparatus for memory abstraction and for word level net list reduction and verification using same Oct 26, 2008 Issued
Array ( [id] => 6580141 [patent_doc_number] => 20100097133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Signal Processing' [patent_app_type] => utility [patent_app_number] => 12/254859 [patent_app_country] => US [patent_app_date] => 2008-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8536 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097133.pdf [firstpage_image] =>[orig_patent_app_number] => 12254859 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/254859
Signal processing Oct 20, 2008 Issued
Array ( [id] => 6630262 [patent_doc_number] => 20100100861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Modifying integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 12/289159 [patent_app_country] => US [patent_app_date] => 2008-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4804 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100861.pdf [firstpage_image] =>[orig_patent_app_number] => 12289159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289159
Modifying integrated circuit layout Oct 20, 2008 Issued
Array ( [id] => 7780258 [patent_doc_number] => 08122405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Delay adjusting method and LSI that uses air-gap wiring' [patent_app_type] => utility [patent_app_number] => 12/253469 [patent_app_country] => US [patent_app_date] => 2008-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8417 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122405.pdf [firstpage_image] =>[orig_patent_app_number] => 12253469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/253469
Delay adjusting method and LSI that uses air-gap wiring Oct 16, 2008 Issued
Array ( [id] => 7553305 [patent_doc_number] => 08065647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Method and system for asynchronous chip design' [patent_app_type] => utility [patent_app_number] => 12/253489 [patent_app_country] => US [patent_app_date] => 2008-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 8230 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065647.pdf [firstpage_image] =>[orig_patent_app_number] => 12253489 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/253489
Method and system for asynchronous chip design Oct 16, 2008 Issued
Array ( [id] => 7537758 [patent_doc_number] => 08051401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Post-routing power supply modification for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/285889 [patent_app_country] => US [patent_app_date] => 2008-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4154 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051401.pdf [firstpage_image] =>[orig_patent_app_number] => 12285889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/285889
Post-routing power supply modification for an integrated circuit Oct 14, 2008 Issued
Array ( [id] => 5363071 [patent_doc_number] => 20090037865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'ROUTER' [patent_app_type] => utility [patent_app_number] => 12/247076 [patent_app_country] => US [patent_app_date] => 2008-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3459 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037865.pdf [firstpage_image] =>[orig_patent_app_number] => 12247076 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/247076
Router Oct 6, 2008 Issued
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