Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7993393 [patent_doc_number] => 08079005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Method and system for performing pattern classification of patterns in integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/241409 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6882 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/079/08079005.pdf [firstpage_image] =>[orig_patent_app_number] => 12241409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/241409
Method and system for performing pattern classification of patterns in integrated circuit designs Sep 29, 2008 Issued
Array ( [id] => 7557522 [patent_doc_number] => 08069432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Method and system for performing statistical leakage characterization, analysis, and modeling' [patent_app_type] => utility [patent_app_number] => 12/241519 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5468 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069432.pdf [firstpage_image] =>[orig_patent_app_number] => 12241519 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/241519
Method and system for performing statistical leakage characterization, analysis, and modeling Sep 29, 2008 Issued
Array ( [id] => 5510473 [patent_doc_number] => 20090083680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'MODEL-BUILDING OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/237069 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11171 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083680.pdf [firstpage_image] =>[orig_patent_app_number] => 12237069 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237069
Model-building optimization Sep 23, 2008 Issued
Array ( [id] => 5510477 [patent_doc_number] => 20090083684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Method for Violating the Logical Function and Timing Behavior of a Digital Circuit Decision' [patent_app_type] => utility [patent_app_number] => 12/233169 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2892 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083684.pdf [firstpage_image] =>[orig_patent_app_number] => 12233169 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233169
Method for validating logical function and timing behavior of a digital circuit decision Sep 17, 2008 Issued
Array ( [id] => 5346235 [patent_doc_number] => 20090001596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'CONDUCTIVE LINE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/211079 [patent_app_country] => US [patent_app_date] => 2008-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2775 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001596.pdf [firstpage_image] =>[orig_patent_app_number] => 12211079 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/211079
CONDUCTIVE LINE STRUCTURE Sep 14, 2008 Abandoned
Array ( [id] => 5454513 [patent_doc_number] => 20090070550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Operational dynamics of three dimensional intelligent system on a chip' [patent_app_type] => utility [patent_app_number] => 12/283454 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11556 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070550.pdf [firstpage_image] =>[orig_patent_app_number] => 12283454 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/283454
Operational dynamics of three dimensional intelligent system on a chip Sep 11, 2008 Abandoned
Array ( [id] => 6621625 [patent_doc_number] => 20100064270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'Cost-Benefit Optimization for an Airgapped Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/208469 [patent_app_country] => US [patent_app_date] => 2008-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064270.pdf [firstpage_image] =>[orig_patent_app_number] => 12208469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/208469
Cost-benefit optimization for an airgapped integrated circuit Sep 10, 2008 Issued
Array ( [id] => 5441460 [patent_doc_number] => 20090093099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Layout method and layout apparatus for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/230629 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6688 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20090093099.pdf [firstpage_image] =>[orig_patent_app_number] => 12230629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/230629
Layout method and layout apparatus for semiconductor integrated circuit Sep 1, 2008 Issued
Array ( [id] => 4509010 [patent_doc_number] => 07958481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof' [patent_app_type] => utility [patent_app_number] => 12/230309 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2760 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958481.pdf [firstpage_image] =>[orig_patent_app_number] => 12230309 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/230309
Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof Aug 26, 2008 Issued
Array ( [id] => 6586932 [patent_doc_number] => 20100047966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/197869 [patent_app_country] => US [patent_app_date] => 2008-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4466 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20100047966.pdf [firstpage_image] =>[orig_patent_app_number] => 12197869 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/197869
Integrated circuit apparatus, systems, and methods Aug 24, 2008 Issued
Array ( [id] => 6492941 [patent_doc_number] => 20100042962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Structure for Couple Noise Characterization Using a Single Oscillator' [patent_app_type] => utility [patent_app_number] => 12/193059 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042962.pdf [firstpage_image] =>[orig_patent_app_number] => 12193059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193059
Structure for couple noise characterization using a single oscillator Aug 17, 2008 Issued
Array ( [id] => 6492934 [patent_doc_number] => 20100042961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'IDENTIFICATION OF VOLTAGE REFERENCE ERRORS IN PCB DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/193119 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1369 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042961.pdf [firstpage_image] =>[orig_patent_app_number] => 12193119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193119
Identification of voltage reference errors in PCB designs Aug 17, 2008 Issued
Array ( [id] => 4511530 [patent_doc_number] => 07949979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-24 [patent_title] => 'Predicting induced crosstalk for the pins of a programmable logic device' [patent_app_type] => utility [patent_app_number] => 12/190729 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949979.pdf [firstpage_image] =>[orig_patent_app_number] => 12190729 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/190729
Predicting induced crosstalk for the pins of a programmable logic device Aug 12, 2008 Issued
Array ( [id] => 7530124 [patent_doc_number] => 08046730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-25 [patent_title] => 'Systems and methods of editing cells of an electronic circuit design' [patent_app_type] => utility [patent_app_number] => 12/222499 [patent_app_country] => US [patent_app_date] => 2008-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 12503 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046730.pdf [firstpage_image] =>[orig_patent_app_number] => 12222499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222499
Systems and methods of editing cells of an electronic circuit design Aug 10, 2008 Issued
Array ( [id] => 4614394 [patent_doc_number] => 07996801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Methods and systems for on-the-fly chip verification' [patent_app_type] => utility [patent_app_number] => 12/188749 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996801.pdf [firstpage_image] =>[orig_patent_app_number] => 12188749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/188749
Methods and systems for on-the-fly chip verification Aug 7, 2008 Issued
Array ( [id] => 6648831 [patent_doc_number] => 20100037196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING INCREMENTAL PLACEMENT IN ELECTRONICS DESIGN' [patent_app_type] => utility [patent_app_number] => 12/188599 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10037 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20100037196.pdf [firstpage_image] =>[orig_patent_app_number] => 12188599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/188599
Method, system, and computer program product for implementing incremental placement in electronics design Aug 7, 2008 Issued
Array ( [id] => 4590180 [patent_doc_number] => 07861201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Method for verifying timing of a circuit with crosstalk victim and aggressor' [patent_app_type] => utility [patent_app_number] => 12/186476 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 11905 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861201.pdf [firstpage_image] =>[orig_patent_app_number] => 12186476 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186476
Method for verifying timing of a circuit with crosstalk victim and aggressor Aug 4, 2008 Issued
Array ( [id] => 5411962 [patent_doc_number] => 20090125861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Wiring design processing method and wiring design processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/222229 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10197 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125861.pdf [firstpage_image] =>[orig_patent_app_number] => 12222229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222229
Wiring design processing method and wiring design processing apparatus Aug 4, 2008 Issued
Array ( [id] => 4951251 [patent_doc_number] => 20080307377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Method for Determining Maximum Operating Frequency of a Filtered Circuit' [patent_app_type] => utility [patent_app_number] => 12/186467 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11847 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307377.pdf [firstpage_image] =>[orig_patent_app_number] => 12186467 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186467
Method for determining maximum operating frequency of a filtered circuit Aug 4, 2008 Issued
Array ( [id] => 4854681 [patent_doc_number] => 20080320425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Method for Verifying Timing of a Circuit with RLC Inputs and Outputs' [patent_app_type] => utility [patent_app_number] => 12/186472 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11868 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320425.pdf [firstpage_image] =>[orig_patent_app_number] => 12186472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186472
Method for verifying timing of a circuit with RLC inputs and outputs Aug 4, 2008 Issued
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