Sun J. Lin

Array ( [id] => 4951250 [patent_doc_number] => 20080307376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Method for Verifying Timing of a Multi-Phase, Multi-Frequency and Multi-Cycle Circuit' [patent_app_type] => utility [patent_app_number] => 12/186444 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11880 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307376.pdf [firstpage_image] =>[orig_patent_app_number] => 12186444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5339322 [patent_doc_number] => 20090055786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Method for Verifying Timing of a Circuit' [patent_app_type] => utility [patent_app_number] => 12/186457 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11866 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055786.pdf [firstpage_image] =>[orig_patent_app_number] => 12186457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5332882 [patent_doc_number] => 20090113359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Model Based Microdevice Design Layout Correction' [patent_app_type] => utility [patent_app_number] => 12/184089 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6316 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113359.pdf [firstpage_image] =>[orig_patent_app_number] => 12184089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4961680 [patent_doc_number] => 20080276105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'POWER MANAGERS FOR AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/176645 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7773 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276105.pdf [firstpage_image] =>[orig_patent_app_number] => 12176645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4854691 [patent_doc_number] => 20080320435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'OPTICAL PROXIMITY CORRECTION IMPROVEMENT BY FRACTURING AFTER PRE-OPTICAL PROXIMITY CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/170471 [patent_app_country] => US [patent_app_date] => 2008-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3557 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320435.pdf [firstpage_image] =>[orig_patent_app_number] => 12170471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 343359 [patent_doc_number] => 07503024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-10 [patent_title] => 'Method for hierarchical VLSI mask layout data interrogation' [patent_app_type] => utility [patent_app_number] => 12/169447 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1301 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/503/07503024.pdf [firstpage_image] =>[orig_patent_app_number] => 12169447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4487583 [patent_doc_number] => 07870528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation' [patent_app_type] => utility [patent_app_number] => 12/168793 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3866 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870528.pdf [firstpage_image] =>[orig_patent_app_number] => 12168793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4862467 [patent_doc_number] => 20080270865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Vendor Independent Method to Merge Coverage Results for Different Designs' [patent_app_type] => utility [patent_app_number] => 12/167958 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270865.pdf [firstpage_image] =>[orig_patent_app_number] => 12167958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5535422 [patent_doc_number] => 20090235210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'ORIENTATION OPTIMIZATION METHOD OF 2-PIN LOGIC CELL' [patent_app_type] => utility [patent_app_number] => 12/147729 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235210.pdf [firstpage_image] =>[orig_patent_app_number] => 12147729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4511577 [patent_doc_number] => 07949989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Methods, systems and computer program products for layout device matching driven by a schematic editor' [patent_app_type] => utility [patent_app_number] => 12/147169 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3754 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949989.pdf [firstpage_image] =>[orig_patent_app_number] => 12147169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5312136 [patent_doc_number] => 20090019417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'LOGIC SYNTHESIS APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/140699 [patent_app_country] => US [patent_app_date] => 2008-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6138 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019417.pdf [firstpage_image] =>[orig_patent_app_number] => 12140699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4626904 [patent_doc_number] => 08006216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-23 [patent_title] => 'Dynamic push for topological routing of semiconductor packages' [patent_app_type] => utility [patent_app_number] => 12/134849 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 8130 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/006/08006216.pdf [firstpage_image] =>[orig_patent_app_number] => 12134849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4616666 [patent_doc_number] => 07992119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-02 [patent_title] => 'Real-time background legality verification of pin placement' [patent_app_type] => utility [patent_app_number] => 12/134999 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6968 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/992/07992119.pdf [firstpage_image] =>[orig_patent_app_number] => 12134999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4739022 [patent_doc_number] => 20080232675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/132710 [patent_app_country] => US [patent_app_date] => 2008-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3458 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232675.pdf [firstpage_image] =>[orig_patent_app_number] => 12132710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4441465 [patent_doc_number] => 07971168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-28 [patent_title] => 'Method for repeated block timing analysis' [patent_app_type] => utility [patent_app_number] => 12/128919 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5255 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971168.pdf [firstpage_image] =>[orig_patent_app_number] => 12128919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500885 [patent_doc_number] => 07904872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'System-on-chip (SOC), design structure and method' [patent_app_type] => utility [patent_app_number] => 12/125255 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6646 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904872.pdf [firstpage_image] =>[orig_patent_app_number] => 12125255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5490462 [patent_doc_number] => 20090291533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'System-On-Chip (SOC), Design Structure and Method' [patent_app_type] => utility [patent_app_number] => 12/125269 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6645 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20090291533.pdf [firstpage_image] =>[orig_patent_app_number] => 12125269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4441474 [patent_doc_number] => 07971171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Method and system for electromigration analysis on signal wiring' [patent_app_type] => utility [patent_app_number] => 12/123769 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5542 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971171.pdf [firstpage_image] =>[orig_patent_app_number] => 12123769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 108162 [patent_doc_number] => 07725862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Signal routing on redistribution layer' [patent_app_type] => utility [patent_app_number] => 12/123701 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2744 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725862.pdf [firstpage_image] =>[orig_patent_app_number] => 12123701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 313471 [patent_doc_number] => 07530041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-05 [patent_title] => 'System and method for auto-routing jog elimination' [patent_app_type] => utility [patent_app_number] => 12/124119 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2798 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530041.pdf [firstpage_image] =>[orig_patent_app_number] => 12124119 [rel_patent_id] =>[rel_patent_doc_number] =>)