Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 313472 [patent_doc_number] => 07530042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-05 [patent_title] => 'System and method for auto-routing jog elimination' [patent_app_type] => utility [patent_app_number] => 12/124120 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2838 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530042.pdf [firstpage_image] =>[orig_patent_app_number] => 12124120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124120
System and method for auto-routing jog elimination May 19, 2008 Issued
Array ( [id] => 4472721 [patent_doc_number] => 07937677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Design-for-test-aware hierarchical design planning' [patent_app_type] => utility [patent_app_number] => 12/123209 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 8519 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937677.pdf [firstpage_image] =>[orig_patent_app_number] => 12123209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123209
Design-for-test-aware hierarchical design planning May 18, 2008 Issued
Array ( [id] => 4780913 [patent_doc_number] => 20080288912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'METHOD OF INSPECTING MASK USING AERIAL IMAGE INSPECTION APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/122399 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288912.pdf [firstpage_image] =>[orig_patent_app_number] => 12122399 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122399
Method of inspecting mask using aerial image inspection apparatus May 15, 2008 Issued
Array ( [id] => 4455166 [patent_doc_number] => 07966597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Method and system for routing of integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/122259 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4702 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966597.pdf [firstpage_image] =>[orig_patent_app_number] => 12122259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122259
Method and system for routing of integrated circuit design May 15, 2008 Issued
Array ( [id] => 5587513 [patent_doc_number] => 20090106715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'Programmable Design Rule Checking' [patent_app_type] => utility [patent_app_number] => 12/121739 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17338 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106715.pdf [firstpage_image] =>[orig_patent_app_number] => 12121739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121739
Programmable Design Rule Checking May 14, 2008 Abandoned
Array ( [id] => 4499561 [patent_doc_number] => 07886241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'System and method for automated electronic device design' [patent_app_type] => utility [patent_app_number] => 12/121206 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9022 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886241.pdf [firstpage_image] =>[orig_patent_app_number] => 12121206 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121206
System and method for automated electronic device design May 14, 2008 Issued
Array ( [id] => 4637066 [patent_doc_number] => 08015531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-06 [patent_title] => 'Deferred parameterization' [patent_app_type] => utility [patent_app_number] => 12/121549 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5059 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015531.pdf [firstpage_image] =>[orig_patent_app_number] => 12121549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121549
Deferred parameterization May 14, 2008 Issued
Array ( [id] => 4678406 [patent_doc_number] => 20080216037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP' [patent_app_type] => utility [patent_app_number] => 12/117841 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2546 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216037.pdf [firstpage_image] =>[orig_patent_app_number] => 12117841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117841
System for using partitioned masks to build a chip May 8, 2008 Issued
Array ( [id] => 4606452 [patent_doc_number] => 07987438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Structure for initializing expansion adapters installed in a computer system having similar expansion adapters' [patent_app_type] => utility [patent_app_number] => 12/113469 [patent_app_country] => US [patent_app_date] => 2008-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9864 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987438.pdf [firstpage_image] =>[orig_patent_app_number] => 12113469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/113469
Structure for initializing expansion adapters installed in a computer system having similar expansion adapters Apr 30, 2008 Issued
Array ( [id] => 343358 [patent_doc_number] => 07503023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-10 [patent_title] => 'Efficient method for locating a short circuit' [patent_app_type] => utility [patent_app_number] => 12/112529 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3581 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/503/07503023.pdf [firstpage_image] =>[orig_patent_app_number] => 12112529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112529
Efficient method for locating a short circuit Apr 29, 2008 Issued
Array ( [id] => 5486974 [patent_doc_number] => 20090276739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'IC CHIP AND DESIGN STRUCTURE INCLUDING STITCHED CIRCUITRY REGION BOUNDARY IDENTIFICATION' [patent_app_type] => utility [patent_app_number] => 12/112336 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5717 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20090276739.pdf [firstpage_image] =>[orig_patent_app_number] => 12112336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112336
IC chip and design structure including stitched circuitry region boundary identification Apr 29, 2008 Issued
Array ( [id] => 5486983 [patent_doc_number] => 20090276748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/112329 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5717 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20090276748.pdf [firstpage_image] =>[orig_patent_app_number] => 12112329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112329
Stitched circuitry region boundary identification for stitched IC chip layout Apr 29, 2008 Issued
Array ( [id] => 4874941 [patent_doc_number] => 20080201675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/111609 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5178 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201675.pdf [firstpage_image] =>[orig_patent_app_number] => 12111609 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111609
Structure for integrated circuit for measuring set-up and hold times for a latch element Apr 28, 2008 Issued
Array ( [id] => 4874947 [patent_doc_number] => 20080201681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE' [patent_app_type] => utility [patent_app_number] => 12/111529 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5441 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201681.pdf [firstpage_image] =>[orig_patent_app_number] => 12111529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111529
Computer program products for determining stopping powers of design structures with respect to a traveling particle Apr 28, 2008 Issued
Array ( [id] => 5560171 [patent_doc_number] => 20090271748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'METHOD AND APPARATUS FOR SIMULATING BEHAVIORAL CONSTRUCTS USING INDETERMINATE VALUES' [patent_app_type] => utility [patent_app_number] => 12/109589 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271748.pdf [firstpage_image] =>[orig_patent_app_number] => 12109589 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/109589
Method and apparatus for simulating behavioral constructs using indeterminate values Apr 24, 2008 Issued
Array ( [id] => 7543004 [patent_doc_number] => 08060853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/108699 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 4829 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060853.pdf [firstpage_image] =>[orig_patent_app_number] => 12108699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108699
Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method and semiconductor device Apr 23, 2008 Issued
Array ( [id] => 4528444 [patent_doc_number] => 07934188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Legalization of VLSI circuit placement with blockages using hierarchical row slicing' [patent_app_type] => utility [patent_app_number] => 12/108599 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4904 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934188.pdf [firstpage_image] =>[orig_patent_app_number] => 12108599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108599
Legalization of VLSI circuit placement with blockages using hierarchical row slicing Apr 23, 2008 Issued
Array ( [id] => 4874951 [patent_doc_number] => 20080201685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Minimizing Number of Masks to be Changed When Changing Existing Connectivity in an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/108199 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201685.pdf [firstpage_image] =>[orig_patent_app_number] => 12108199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108199
Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit Apr 22, 2008 Issued
Array ( [id] => 8581030 [patent_doc_number] => 08347262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Method of deriving an integrated circuit schematic diagram' [patent_app_type] => utility [patent_app_number] => 12/989739 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5601 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12989739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/989739
Method of deriving an integrated circuit schematic diagram Apr 17, 2008 Issued
Array ( [id] => 7972403 [patent_doc_number] => 07941780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Intersect area based ground rule for semiconductor design' [patent_app_type] => utility [patent_app_number] => 12/105299 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8439 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941780.pdf [firstpage_image] =>[orig_patent_app_number] => 12105299 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105299
Intersect area based ground rule for semiconductor design Apr 17, 2008 Issued
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