Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4499610 [patent_doc_number] => 07886250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Reconfigurable integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/103229 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 4236 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886250.pdf [firstpage_image] =>[orig_patent_app_number] => 12103229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/103229
Reconfigurable integrated circuit Apr 14, 2008 Issued
Array ( [id] => 4684155 [patent_doc_number] => 20080250381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/062859 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250381.pdf [firstpage_image] =>[orig_patent_app_number] => 12062859 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062859
Parameter adjustment method, semiconductor device manufacturing method, and recording medium Apr 3, 2008 Issued
Array ( [id] => 4678399 [patent_doc_number] => 20080216030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'System for Performing Verification of Logic Circuits' [patent_app_type] => utility [patent_app_number] => 12/060953 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5621 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216030.pdf [firstpage_image] =>[orig_patent_app_number] => 12060953 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060953
System for performing verification of logic circuits Apr 1, 2008 Issued
Array ( [id] => 351035 [patent_doc_number] => 07496885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-24 [patent_title] => 'Method of compensating for defective pattern generation data in a variable shaped electron beam system' [patent_app_type] => utility [patent_app_number] => 12/061439 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1585 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/496/07496885.pdf [firstpage_image] =>[orig_patent_app_number] => 12061439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/061439
Method of compensating for defective pattern generation data in a variable shaped electron beam system Apr 1, 2008 Issued
Array ( [id] => 5476101 [patent_doc_number] => 20090249267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'CONSTRAINED RANDOM SIMULATION COVERAGE CLOSURE GUIDED BY A COVER PROPERTY' [patent_app_type] => utility [patent_app_number] => 12/059096 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4051 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20090249267.pdf [firstpage_image] =>[orig_patent_app_number] => 12059096 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059096
Constrained random simulation coverage closure guided by a cover property Mar 30, 2008 Issued
Array ( [id] => 4443771 [patent_doc_number] => 07900172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method and apparatus for analyzing power consumption' [patent_app_type] => utility [patent_app_number] => 12/058339 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3698 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900172.pdf [firstpage_image] =>[orig_patent_app_number] => 12058339 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/058339
Method and apparatus for analyzing power consumption Mar 27, 2008 Issued
Array ( [id] => 7553311 [patent_doc_number] => 08065653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-22 [patent_title] => 'Configuration of programmable IC design elements' [patent_app_type] => utility [patent_app_number] => 12/058569 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3035 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065653.pdf [firstpage_image] =>[orig_patent_app_number] => 12058569 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/058569
Configuration of programmable IC design elements Mar 27, 2008 Issued
Array ( [id] => 4550803 [patent_doc_number] => 07873931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-18 [patent_title] => 'Congestion-based routing with reconfigurable cross-points for dense signal tapping' [patent_app_type] => utility [patent_app_number] => 12/053059 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/873/07873931.pdf [firstpage_image] =>[orig_patent_app_number] => 12053059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053059
Congestion-based routing with reconfigurable cross-points for dense signal tapping Mar 20, 2008 Issued
Array ( [id] => 4558512 [patent_doc_number] => 07890899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Variable clocked scan test improvements' [patent_app_type] => utility [patent_app_number] => 12/046336 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 12458 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890899.pdf [firstpage_image] =>[orig_patent_app_number] => 12046336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/046336
Variable clocked scan test improvements Mar 10, 2008 Issued
Array ( [id] => 4698192 [patent_doc_number] => 20080220376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'LITHOGRAPHY SIMULATION METHOD, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/042879 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4621 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20080220376.pdf [firstpage_image] =>[orig_patent_app_number] => 12042879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042879
Lithography simulation method, method of manufacturing a semiconductor device and program Mar 4, 2008 Issued
Array ( [id] => 5387598 [patent_doc_number] => 20090228843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT' [patent_app_type] => utility [patent_app_number] => 12/041729 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2494 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228843.pdf [firstpage_image] =>[orig_patent_app_number] => 12041729 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041729
Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point Mar 3, 2008 Issued
Array ( [id] => 4470504 [patent_doc_number] => 07882478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Spacers for reducing crosstalk and maintaining clearances' [patent_app_type] => utility [patent_app_number] => 12/039389 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882478.pdf [firstpage_image] =>[orig_patent_app_number] => 12039389 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039389
Spacers for reducing crosstalk and maintaining clearances Feb 27, 2008 Issued
Array ( [id] => 4443792 [patent_doc_number] => 07900178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Integrated circuit (IC) design method, system and program product' [patent_app_type] => utility [patent_app_number] => 12/039109 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2624 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900178.pdf [firstpage_image] =>[orig_patent_app_number] => 12039109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039109
Integrated circuit (IC) design method, system and program product Feb 27, 2008 Issued
Array ( [id] => 4700402 [patent_doc_number] => 20080222586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Delay analysis apparatus, delay analysis method and computer product' [patent_app_type] => utility [patent_app_number] => 12/073039 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222586.pdf [firstpage_image] =>[orig_patent_app_number] => 12073039 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073039
Delay analysis apparatus, delay analysis method and computer product Feb 27, 2008 Issued
Array ( [id] => 4508926 [patent_doc_number] => 07958468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Unidirectional relabeling for subcircuit recognition' [patent_app_type] => utility [patent_app_number] => 12/035409 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958468.pdf [firstpage_image] =>[orig_patent_app_number] => 12035409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035409
Unidirectional relabeling for subcircuit recognition Feb 20, 2008 Issued
Array ( [id] => 4614402 [patent_doc_number] => 07996809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Software controlled transistor body bias' [patent_app_type] => utility [patent_app_number] => 12/033832 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6118 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996809.pdf [firstpage_image] =>[orig_patent_app_number] => 12033832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033832
Software controlled transistor body bias Feb 18, 2008 Issued
Array ( [id] => 4592942 [patent_doc_number] => 07853918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Reverse dummy insertion algorithm' [patent_app_type] => utility [patent_app_number] => 12/013999 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853918.pdf [firstpage_image] =>[orig_patent_app_number] => 12013999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013999
Reverse dummy insertion algorithm Jan 13, 2008 Issued
Array ( [id] => 4592942 [patent_doc_number] => 07853918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Reverse dummy insertion algorithm' [patent_app_type] => utility [patent_app_number] => 12/013999 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853918.pdf [firstpage_image] =>[orig_patent_app_number] => 12013999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013999
Reverse dummy insertion algorithm Jan 13, 2008 Issued
Array ( [id] => 4592942 [patent_doc_number] => 07853918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Reverse dummy insertion algorithm' [patent_app_type] => utility [patent_app_number] => 12/013999 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853918.pdf [firstpage_image] =>[orig_patent_app_number] => 12013999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013999
Reverse dummy insertion algorithm Jan 13, 2008 Issued
Array ( [id] => 4592942 [patent_doc_number] => 07853918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Reverse dummy insertion algorithm' [patent_app_type] => utility [patent_app_number] => 12/013999 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853918.pdf [firstpage_image] =>[orig_patent_app_number] => 12013999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013999
Reverse dummy insertion algorithm Jan 13, 2008 Issued
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