Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4487528 [patent_doc_number] => 07870520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Semiconductor device and yield calculation method' [patent_app_type] => utility [patent_app_number] => 11/972709 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 10808 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870520.pdf [firstpage_image] =>[orig_patent_app_number] => 11972709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972709
Semiconductor device and yield calculation method Jan 10, 2008 Issued
Array ( [id] => 4843346 [patent_doc_number] => 20080179754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/007439 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179754.pdf [firstpage_image] =>[orig_patent_app_number] => 12007439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/007439
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device Jan 9, 2008 Issued
Array ( [id] => 9364 [patent_doc_number] => 07814450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Active skew control of a digital phase-lock loop using delay lock-loops' [patent_app_type] => utility [patent_app_number] => 11/967079 [patent_app_country] => US [patent_app_date] => 2007-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2042 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/814/07814450.pdf [firstpage_image] =>[orig_patent_app_number] => 11967079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967079
Active skew control of a digital phase-lock loop using delay lock-loops Dec 28, 2007 Issued
Array ( [id] => 4678409 [patent_doc_number] => 20080216040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Incremental Relative Slack Timing Force Model' [patent_app_type] => utility [patent_app_number] => 11/967179 [patent_app_country] => US [patent_app_date] => 2007-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 51493 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216040.pdf [firstpage_image] =>[orig_patent_app_number] => 11967179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967179
Incremental relative slack timing force model Dec 28, 2007 Issued
Array ( [id] => 4550739 [patent_doc_number] => 07926005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-12 [patent_title] => 'Pattern-driven routing' [patent_app_type] => utility [patent_app_number] => 11/966689 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4275 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/926/07926005.pdf [firstpage_image] =>[orig_patent_app_number] => 11966689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966689
Pattern-driven routing Dec 27, 2007 Issued
Array ( [id] => 69200 [patent_doc_number] => 07761820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Automated migration of analog and mixed-signal VLSI design' [patent_app_type] => utility [patent_app_number] => 11/964757 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 11397 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761820.pdf [firstpage_image] =>[orig_patent_app_number] => 11964757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964757
Automated migration of analog and mixed-signal VLSI design Dec 26, 2007 Issued
Array ( [id] => 4966384 [patent_doc_number] => 20080109204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'MOSFET Modeling for IC Design Accurate for High Frequencies' [patent_app_type] => utility [patent_app_number] => 11/959068 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11576 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109204.pdf [firstpage_image] =>[orig_patent_app_number] => 11959068 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959068
MOSFET modeling for IC design accurate for high frequencies Dec 17, 2007 Issued
Array ( [id] => 4866710 [patent_doc_number] => 20080145769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'SIMULATION METHOD, SIMULATION SYSTEM, AND METHOD OF CORRECTING MASK PATTERN' [patent_app_type] => utility [patent_app_number] => 11/956439 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7160 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20080145769.pdf [firstpage_image] =>[orig_patent_app_number] => 11956439 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956439
SIMULATION METHOD, SIMULATION SYSTEM, AND METHOD OF CORRECTING MASK PATTERN Dec 13, 2007 Abandoned
Array ( [id] => 4590504 [patent_doc_number] => 07831939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Semiconductor integrated circuit device featuring processed minimum circuit pattern, and design method therefor' [patent_app_type] => utility [patent_app_number] => 11/950549 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7597 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831939.pdf [firstpage_image] =>[orig_patent_app_number] => 11950549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950549
Semiconductor integrated circuit device featuring processed minimum circuit pattern, and design method therefor Dec 4, 2007 Issued
Array ( [id] => 4895455 [patent_doc_number] => 20080104555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN' [patent_app_type] => utility [patent_app_number] => 11/947254 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6050 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104555.pdf [firstpage_image] =>[orig_patent_app_number] => 11947254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947254
Testing pattern sensitive algorithms for semiconductor design Nov 28, 2007 Issued
Array ( [id] => 4590532 [patent_doc_number] => 07831947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Semiconductor layout design apparatus, semiconductor layout design method and computer readable medium' [patent_app_type] => utility [patent_app_number] => 11/941739 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831947.pdf [firstpage_image] =>[orig_patent_app_number] => 11941739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941739
Semiconductor layout design apparatus, semiconductor layout design method and computer readable medium Nov 15, 2007 Issued
Array ( [id] => 38578 [patent_doc_number] => 07788616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and system for performing heuristic constraint simplification' [patent_app_type] => utility [patent_app_number] => 11/940755 [patent_app_country] => US [patent_app_date] => 2007-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5032 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788616.pdf [firstpage_image] =>[orig_patent_app_number] => 11940755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940755
Method and system for performing heuristic constraint simplification Nov 14, 2007 Issued
Array ( [id] => 37838 [patent_doc_number] => 07793242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method and system for performing heuristic constraint simplification' [patent_app_type] => utility [patent_app_number] => 11/940711 [patent_app_country] => US [patent_app_date] => 2007-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5033 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793242.pdf [firstpage_image] =>[orig_patent_app_number] => 11940711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940711
Method and system for performing heuristic constraint simplification Nov 14, 2007 Issued
Array ( [id] => 4691956 [patent_doc_number] => 20080084726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Semiconductor integrated circuit device and method for designing the same' [patent_app_type] => utility [patent_app_number] => 11/980461 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15662 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20080084726.pdf [firstpage_image] =>[orig_patent_app_number] => 11980461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980461
Semiconductor integrated circuit device and method for designing the same Oct 30, 2007 Abandoned
Array ( [id] => 4919240 [patent_doc_number] => 20080067552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Semiconductor integrated circuit device and method for desiging the same' [patent_app_type] => utility [patent_app_number] => 11/980562 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15660 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067552.pdf [firstpage_image] =>[orig_patent_app_number] => 11980562 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980562
Semiconductor integrated circuit device and method for desiging the same Oct 30, 2007 Abandoned
Array ( [id] => 4937596 [patent_doc_number] => 20080074913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Semiconductor integrated circuit device and method for designing the same' [patent_app_type] => utility [patent_app_number] => 11/980589 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15661 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074913.pdf [firstpage_image] =>[orig_patent_app_number] => 11980589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980589
Semiconductor integrated circuit device and method for designing the same Oct 30, 2007 Abandoned
Array ( [id] => 37822 [patent_doc_number] => 07793235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method and circuit for matching semiconductor device behavior' [patent_app_type] => utility [patent_app_number] => 11/923739 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4853 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793235.pdf [firstpage_image] =>[orig_patent_app_number] => 11923739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923739
Method and circuit for matching semiconductor device behavior Oct 24, 2007 Issued
Array ( [id] => 4917040 [patent_doc_number] => 20080097641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Interconnect structure of semiconductor integrated circuit, and design method and device therefor' [patent_app_type] => utility [patent_app_number] => 11/907999 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10185 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20080097641.pdf [firstpage_image] =>[orig_patent_app_number] => 11907999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907999
Interconnect structure of semiconductor integrated circuit, and design method and device therefor Oct 18, 2007 Issued
Array ( [id] => 4653439 [patent_doc_number] => 20080040696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2' [patent_app_type] => utility [patent_app_number] => 11/875069 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3010 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040696.pdf [firstpage_image] =>[orig_patent_app_number] => 11875069 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/875069
Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2 Oct 18, 2007 Abandoned
Array ( [id] => 5587507 [patent_doc_number] => 20090106709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'System for Improving a Logic Circuit and Associated Methods' [patent_app_type] => utility [patent_app_number] => 11/873919 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106709.pdf [firstpage_image] =>[orig_patent_app_number] => 11873919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873919
System for improving a logic circuit and associated methods Oct 16, 2007 Issued
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