Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5286719 [patent_doc_number] => 20090100394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Method, Apparatus, and Computer Program Product for Automatically Waiving Non-Compute Indications for a Timing Analysis Process' [patent_app_type] => utility [patent_app_number] => 11/871179 [patent_app_country] => US [patent_app_date] => 2007-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20090100394.pdf [firstpage_image] =>[orig_patent_app_number] => 11871179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/871179
Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process Oct 11, 2007 Issued
Array ( [id] => 19196 [patent_doc_number] => 07810066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Irradiation pattern data generation method, mask fabrication method, and plotting system' [patent_app_type] => utility [patent_app_number] => 11/866699 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 9143 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/810/07810066.pdf [firstpage_image] =>[orig_patent_app_number] => 11866699 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866699
Irradiation pattern data generation method, mask fabrication method, and plotting system Oct 2, 2007 Issued
Array ( [id] => 5430424 [patent_doc_number] => 20090089734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD FOR FASTER IDENTIFICATION OF AVAILABLE REFERENCE DESIGNATORS IN A DESIGN AUTOMATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/866159 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4445 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089734.pdf [firstpage_image] =>[orig_patent_app_number] => 11866159 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866159
Method for fast identification of available reference designators in a design automation system Oct 1, 2007 Issued
Array ( [id] => 4837149 [patent_doc_number] => 20080134124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/905129 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134124.pdf [firstpage_image] =>[orig_patent_app_number] => 11905129 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905129
Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method Sep 26, 2007 Issued
Array ( [id] => 6334232 [patent_doc_number] => 20100198573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SIGNAL SELECTING APPARATUS, CIRCUIT AMENDING APPARATUS, CIRCUIT SIMULATOR, CIRCUIT EMULATOR, METHOD OF SIGNAL SELECTION AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/311249 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8980 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20100198573.pdf [firstpage_image] =>[orig_patent_app_number] => 12311249 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/311249
Signal selecting apparatus, circuit amending apparatus, circuit simulator, circuit emulator, method of signal selection and program Sep 24, 2007 Issued
Array ( [id] => 4869175 [patent_doc_number] => 20080148205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Circuit delay analyzer, circuit delay analyzing method, and computer product' [patent_app_type] => utility [patent_app_number] => 11/902489 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6120 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148205.pdf [firstpage_image] =>[orig_patent_app_number] => 11902489 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902489
Circuit delay analyzer, circuit delay analyzing method, and computer product Sep 20, 2007 Issued
Array ( [id] => 4799039 [patent_doc_number] => 20080010625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'AUTO CONNECTION ASSIGNMENT SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 11/858995 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20080010625.pdf [firstpage_image] =>[orig_patent_app_number] => 11858995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858995
Auto connection assignment system and method Sep 20, 2007 Issued
Array ( [id] => 4923865 [patent_doc_number] => 20080072182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'STRUCTURED AND PARAMETERIZED MODEL ORDER REDUCTION' [patent_app_type] => utility [patent_app_number] => 11/858099 [patent_app_country] => US [patent_app_date] => 2007-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 26284 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072182.pdf [firstpage_image] =>[orig_patent_app_number] => 11858099 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858099
STRUCTURED AND PARAMETERIZED MODEL ORDER REDUCTION Sep 18, 2007 Abandoned
Array ( [id] => 4587368 [patent_doc_number] => 07849434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/852320 [patent_app_country] => US [patent_app_date] => 2007-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 10127 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849434.pdf [firstpage_image] =>[orig_patent_app_number] => 11852320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/852320
Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Sep 8, 2007 Issued
Array ( [id] => 128319 [patent_doc_number] => 07707535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Stitched IC chip layout design structure' [patent_app_type] => utility [patent_app_number] => 11/849461 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6599 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707535.pdf [firstpage_image] =>[orig_patent_app_number] => 11849461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849461
Stitched IC chip layout design structure Sep 3, 2007 Issued
Array ( [id] => 97138 [patent_doc_number] => 07735039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-08 [patent_title] => 'Methods of estimating net delays in tile-based PLD architectures' [patent_app_type] => utility [patent_app_number] => 11/895899 [patent_app_country] => US [patent_app_date] => 2007-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/735/07735039.pdf [firstpage_image] =>[orig_patent_app_number] => 11895899 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/895899
Methods of estimating net delays in tile-based PLD architectures Aug 27, 2007 Issued
Array ( [id] => 4659495 [patent_doc_number] => 20080028357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'METHOD OF AUTOMATIC GENERATION OF MICRO CLOCK GATING FOR REDUCING POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 11/830069 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4353 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028357.pdf [firstpage_image] =>[orig_patent_app_number] => 11830069 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830069
METHOD OF AUTOMATIC GENERATION OF MICRO CLOCK GATING FOR REDUCING POWER CONSUMPTION Jul 29, 2007 Abandoned
Array ( [id] => 5523289 [patent_doc_number] => 20090031270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Design Method and System for Minimizing Blind Via Current Loops' [patent_app_type] => utility [patent_app_number] => 11/829179 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3599 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031270.pdf [firstpage_image] =>[orig_patent_app_number] => 11829179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829179
Design method and system for minimizing blind via current loops Jul 26, 2007 Issued
Array ( [id] => 69213 [patent_doc_number] => 07761826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Method and system for crosstalk analysis' [patent_app_type] => utility [patent_app_number] => 11/782619 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761826.pdf [firstpage_image] =>[orig_patent_app_number] => 11782619 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782619
Method and system for crosstalk analysis Jul 23, 2007 Issued
Array ( [id] => 4730914 [patent_doc_number] => 20080209378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD AND SYSTEM FOR PROTOTYPING ELECTRONIC DEVICES WITH MULTI-CONFIGURATION CHIP CARRIERS' [patent_app_type] => utility [patent_app_number] => 11/780919 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6051 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209378.pdf [firstpage_image] =>[orig_patent_app_number] => 11780919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780919
Method and system for prototyping electronic devices with multi-configuration CHIP carriers Jul 19, 2007 Issued
Array ( [id] => 5232548 [patent_doc_number] => 20070294657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'METHODS AND APPARATUS FOR DEFINING MANHATTAN POWER GRID STRUCTURES HAVING A REDUCED NUMBER OF VIAS' [patent_app_type] => utility [patent_app_number] => 11/780459 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9402 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20070294657.pdf [firstpage_image] =>[orig_patent_app_number] => 11780459 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780459
Methods and apparatus for defining manhattan power grid structures having a reduced number of vias Jul 18, 2007 Issued
Array ( [id] => 4911484 [patent_doc_number] => 20080022251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'INTERACTIVE SCHEMATIC FOR USE IN ANALOG, MIXED-SIGNAL, AND CUSTOM DIGITAL CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 11/780039 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5950 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20080022251.pdf [firstpage_image] =>[orig_patent_app_number] => 11780039 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780039
Interactive schematic for use in analog, mixed-signal, and custom digital circuit design Jul 18, 2007 Issued
Array ( [id] => 5305918 [patent_doc_number] => 20090300570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'INTERACTIVE HIERARCHICAL ANALOG LAYOUT SYNTHESIS FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/307562 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13221 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300570.pdf [firstpage_image] =>[orig_patent_app_number] => 12307562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/307562
INTERACTIVE HIERARCHICAL ANALOG LAYOUT SYNTHESIS FOR INTEGRATED CIRCUITS Jul 15, 2007 Abandoned
Array ( [id] => 4722865 [patent_doc_number] => 20080244480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'System and method to generate an IC layout using simplified manufacturing rule' [patent_app_type] => utility [patent_app_number] => 11/824759 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2701 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244480.pdf [firstpage_image] =>[orig_patent_app_number] => 11824759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/824759
System and method to generate an IC layout using simplified manufacturing rule Jul 1, 2007 Issued
Array ( [id] => 69199 [patent_doc_number] => 07761819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'System and method of modification of integrated circuit mask layout' [patent_app_type] => utility [patent_app_number] => 11/824749 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4279 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761819.pdf [firstpage_image] =>[orig_patent_app_number] => 11824749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/824749
System and method of modification of integrated circuit mask layout Jul 1, 2007 Issued
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