
Sun J. Lin
Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 1569 |
| Issued Applications | 1454 |
| Pending Applications | 15 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5286719
[patent_doc_number] => 20090100394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'Method, Apparatus, and Computer Program Product for Automatically Waiving Non-Compute Indications for a Timing Analysis Process'
[patent_app_type] => utility
[patent_app_number] => 11/871179
[patent_app_country] => US
[patent_app_date] => 2007-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20090100394.pdf
[firstpage_image] =>[orig_patent_app_number] => 11871179
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/871179 | Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process | Oct 11, 2007 | Issued |
Array
(
[id] => 19196
[patent_doc_number] => 07810066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-05
[patent_title] => 'Irradiation pattern data generation method, mask fabrication method, and plotting system'
[patent_app_type] => utility
[patent_app_number] => 11/866699
[patent_app_country] => US
[patent_app_date] => 2007-10-03
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/810/07810066.pdf
[firstpage_image] =>[orig_patent_app_number] => 11866699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/866699 | Irradiation pattern data generation method, mask fabrication method, and plotting system | Oct 2, 2007 | Issued |
Array
(
[id] => 5430424
[patent_doc_number] => 20090089734
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'METHOD FOR FASTER IDENTIFICATION OF AVAILABLE REFERENCE DESIGNATORS IN A DESIGN AUTOMATION SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/866159
[patent_app_country] => US
[patent_app_date] => 2007-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0089/20090089734.pdf
[firstpage_image] =>[orig_patent_app_number] => 11866159
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/866159 | Method for fast identification of available reference designators in a design automation system | Oct 1, 2007 | Issued |
Array
(
[id] => 4837149
[patent_doc_number] => 20080134124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/905129
[patent_app_country] => US
[patent_app_date] => 2007-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[firstpage_image] =>[orig_patent_app_number] => 11905129
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/905129 | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method | Sep 26, 2007 | Issued |
Array
(
[id] => 6334232
[patent_doc_number] => 20100198573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-05
[patent_title] => 'SIGNAL SELECTING APPARATUS, CIRCUIT AMENDING APPARATUS, CIRCUIT SIMULATOR, CIRCUIT EMULATOR, METHOD OF SIGNAL SELECTION AND PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/311249
[patent_app_country] => US
[patent_app_date] => 2007-09-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0198/20100198573.pdf
[firstpage_image] =>[orig_patent_app_number] => 12311249
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/311249 | Signal selecting apparatus, circuit amending apparatus, circuit simulator, circuit emulator, method of signal selection and program | Sep 24, 2007 | Issued |
Array
(
[id] => 4869175
[patent_doc_number] => 20080148205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'Circuit delay analyzer, circuit delay analyzing method, and computer product'
[patent_app_type] => utility
[patent_app_number] => 11/902489
[patent_app_country] => US
[patent_app_date] => 2007-09-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0148/20080148205.pdf
[firstpage_image] =>[orig_patent_app_number] => 11902489
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/902489 | Circuit delay analyzer, circuit delay analyzing method, and computer product | Sep 20, 2007 | Issued |
Array
(
[id] => 4799039
[patent_doc_number] => 20080010625
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'AUTO CONNECTION ASSIGNMENT SYSTEM AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/858995
[patent_app_country] => US
[patent_app_date] => 2007-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5754
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[pdf_file] => publications/A1/0010/20080010625.pdf
[firstpage_image] =>[orig_patent_app_number] => 11858995
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/858995 | Auto connection assignment system and method | Sep 20, 2007 | Issued |
Array
(
[id] => 4923865
[patent_doc_number] => 20080072182
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'STRUCTURED AND PARAMETERIZED MODEL ORDER REDUCTION'
[patent_app_type] => utility
[patent_app_number] => 11/858099
[patent_app_country] => US
[patent_app_date] => 2007-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
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[patent_no_of_words] => 26284
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[pdf_file] => publications/A1/0072/20080072182.pdf
[firstpage_image] =>[orig_patent_app_number] => 11858099
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/858099 | STRUCTURED AND PARAMETERIZED MODEL ORDER REDUCTION | Sep 18, 2007 | Abandoned |
Array
(
[id] => 4587368
[patent_doc_number] => 07849434
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-07
[patent_title] => 'Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/852320
[patent_app_country] => US
[patent_app_date] => 2007-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
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[patent_no_of_words] => 10127
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/849/07849434.pdf
[firstpage_image] =>[orig_patent_app_number] => 11852320
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/852320 | Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit | Sep 8, 2007 | Issued |
Array
(
[id] => 128319
[patent_doc_number] => 07707535
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-27
[patent_title] => 'Stitched IC chip layout design structure'
[patent_app_type] => utility
[patent_app_number] => 11/849461
[patent_app_country] => US
[patent_app_date] => 2007-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/07/707/07707535.pdf
[firstpage_image] =>[orig_patent_app_number] => 11849461
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/849461 | Stitched IC chip layout design structure | Sep 3, 2007 | Issued |
Array
(
[id] => 97138
[patent_doc_number] => 07735039
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-06-08
[patent_title] => 'Methods of estimating net delays in tile-based PLD architectures'
[patent_app_type] => utility
[patent_app_number] => 11/895899
[patent_app_country] => US
[patent_app_date] => 2007-08-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/735/07735039.pdf
[firstpage_image] =>[orig_patent_app_number] => 11895899
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/895899 | Methods of estimating net delays in tile-based PLD architectures | Aug 27, 2007 | Issued |
Array
(
[id] => 4659495
[patent_doc_number] => 20080028357
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'METHOD OF AUTOMATIC GENERATION OF MICRO CLOCK GATING FOR REDUCING POWER CONSUMPTION'
[patent_app_type] => utility
[patent_app_number] => 11/830069
[patent_app_country] => US
[patent_app_date] => 2007-07-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0028/20080028357.pdf
[firstpage_image] =>[orig_patent_app_number] => 11830069
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/830069 | METHOD OF AUTOMATIC GENERATION OF MICRO CLOCK GATING FOR REDUCING POWER CONSUMPTION | Jul 29, 2007 | Abandoned |
Array
(
[id] => 5523289
[patent_doc_number] => 20090031270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-29
[patent_title] => 'Design Method and System for Minimizing Blind Via Current Loops'
[patent_app_type] => utility
[patent_app_number] => 11/829179
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[pdf_file] => publications/A1/0031/20090031270.pdf
[firstpage_image] =>[orig_patent_app_number] => 11829179
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/829179 | Design method and system for minimizing blind via current loops | Jul 26, 2007 | Issued |
Array
(
[id] => 69213
[patent_doc_number] => 07761826
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-07-20
[patent_title] => 'Method and system for crosstalk analysis'
[patent_app_type] => utility
[patent_app_number] => 11/782619
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/782619 | Method and system for crosstalk analysis | Jul 23, 2007 | Issued |
Array
(
[id] => 4730914
[patent_doc_number] => 20080209378
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[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'METHOD AND SYSTEM FOR PROTOTYPING ELECTRONIC DEVICES WITH MULTI-CONFIGURATION CHIP CARRIERS'
[patent_app_type] => utility
[patent_app_number] => 11/780919
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11780919
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/780919 | Method and system for prototyping electronic devices with multi-configuration CHIP carriers | Jul 19, 2007 | Issued |
Array
(
[id] => 5232548
[patent_doc_number] => 20070294657
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'METHODS AND APPARATUS FOR DEFINING MANHATTAN POWER GRID STRUCTURES HAVING A REDUCED NUMBER OF VIAS'
[patent_app_type] => utility
[patent_app_number] => 11/780459
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[patent_app_date] => 2007-07-19
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[firstpage_image] =>[orig_patent_app_number] => 11780459
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/780459 | Methods and apparatus for defining manhattan power grid structures having a reduced number of vias | Jul 18, 2007 | Issued |
Array
(
[id] => 4911484
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[patent_title] => 'INTERACTIVE SCHEMATIC FOR USE IN ANALOG, MIXED-SIGNAL, AND CUSTOM DIGITAL CIRCUIT DESIGN'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/780039 | Interactive schematic for use in analog, mixed-signal, and custom digital circuit design | Jul 18, 2007 | Issued |
Array
(
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[patent_title] => 'INTERACTIVE HIERARCHICAL ANALOG LAYOUT SYNTHESIS FOR INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 12/307562
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/307562 | INTERACTIVE HIERARCHICAL ANALOG LAYOUT SYNTHESIS FOR INTEGRATED CIRCUITS | Jul 15, 2007 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/824759 | System and method to generate an IC layout using simplified manufacturing rule | Jul 1, 2007 | Issued |
Array
(
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[patent_title] => 'System and method of modification of integrated circuit mask layout'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/824749 | System and method of modification of integrated circuit mask layout | Jul 1, 2007 | Issued |