Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 38584 [patent_doc_number] => 07788619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Memories, memory compiling systems and methods for the same' [patent_app_type] => utility [patent_app_number] => 11/819389 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6644 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788619.pdf [firstpage_image] =>[orig_patent_app_number] => 11819389 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819389
Memories, memory compiling systems and methods for the same Jun 26, 2007 Issued
Array ( [id] => 4804894 [patent_doc_number] => 20080016483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'HIERARCHICAL ANALOG LAYOUT SYNTHESIS AND OPTIMIZATION FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/757349 [patent_app_country] => US [patent_app_date] => 2007-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8149 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016483.pdf [firstpage_image] =>[orig_patent_app_number] => 11757349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/757349
Hierarchical analog layout synthesis and optimization for integrated circuits Jun 1, 2007 Issued
Array ( [id] => 268646 [patent_doc_number] => 07568175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Ramptime propagation on designs with cycles' [patent_app_type] => utility [patent_app_number] => 11/757229 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5739 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/568/07568175.pdf [firstpage_image] =>[orig_patent_app_number] => 11757229 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/757229
Ramptime propagation on designs with cycles May 31, 2007 Issued
Array ( [id] => 4693942 [patent_doc_number] => 20080086713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'METHOD AND APPARATUS FOR AUTOMATIC SYNTHESIS OF AN ELECTRONIC CIRCUIT MODEL' [patent_app_type] => utility [patent_app_number] => 11/756129 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13066 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086713.pdf [firstpage_image] =>[orig_patent_app_number] => 11756129 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/756129
Method and apparatus for automatic synthesis of an electronic circuit model May 30, 2007 Issued
Array ( [id] => 58368 [patent_doc_number] => 07774727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/755269 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 18543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774727.pdf [firstpage_image] =>[orig_patent_app_number] => 11755269 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/755269
Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device May 29, 2007 Issued
Array ( [id] => 5577323 [patent_doc_number] => 20090144685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'DOUBLE-LAYER INTEGRAL USING A STATIC GREEN\'S FUNCTION AND RECTANGULAR BASIS' [patent_app_type] => utility [patent_app_number] => 11/754539 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2972 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144685.pdf [firstpage_image] =>[orig_patent_app_number] => 11754539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/754539
DOUBLE-LAYER INTEGRAL USING A STATIC GREEN'S FUNCTION AND RECTANGULAR BASIS May 28, 2007 Abandoned
Array ( [id] => 4665590 [patent_doc_number] => 20080256497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Scan compression circuit and method of design therefor' [patent_app_type] => utility [patent_app_number] => 11/807119 [patent_app_country] => US [patent_app_date] => 2007-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15287 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256497.pdf [firstpage_image] =>[orig_patent_app_number] => 11807119 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/807119
Scan compression circuit and method of design therefor May 24, 2007 Issued
Array ( [id] => 66673 [patent_doc_number] => 07765498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-27 [patent_title] => 'Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist' [patent_app_type] => utility [patent_app_number] => 11/805739 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4599 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765498.pdf [firstpage_image] =>[orig_patent_app_number] => 11805739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805739
Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist May 23, 2007 Issued
Array ( [id] => 816708 [patent_doc_number] => 07415695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'System for search and analysis of systematic defects in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/748575 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3459 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415695.pdf [firstpage_image] =>[orig_patent_app_number] => 11748575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/748575
System for search and analysis of systematic defects in integrated circuits May 14, 2007 Issued
Array ( [id] => 17608 [patent_doc_number] => 07805692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Method for local hot spot fixing' [patent_app_type] => utility [patent_app_number] => 11/748599 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 10226 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805692.pdf [firstpage_image] =>[orig_patent_app_number] => 11748599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/748599
Method for local hot spot fixing May 14, 2007 Issued
Array ( [id] => 108157 [patent_doc_number] => 07725857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method for optimizing organizational floor layout and operations' [patent_app_type] => utility [patent_app_number] => 11/737309 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725857.pdf [firstpage_image] =>[orig_patent_app_number] => 11737309 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/737309
Method for optimizing organizational floor layout and operations Apr 18, 2007 Issued
Array ( [id] => 4684152 [patent_doc_number] => 20080250378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'CIRCUIT EMULATION AND DEBUGGING METHOD' [patent_app_type] => utility [patent_app_number] => 11/697869 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4492 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250378.pdf [firstpage_image] =>[orig_patent_app_number] => 11697869 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697869
Circuit emulation and debugging method Apr 8, 2007 Issued
Array ( [id] => 4684151 [patent_doc_number] => 20080250377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'CONDUCTIVE DOME PROBES FOR MEASURING SYSTEM LEVEL MULTI-GHZ SIGNALS' [patent_app_type] => utility [patent_app_number] => 11/696659 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250377.pdf [firstpage_image] =>[orig_patent_app_number] => 11696659 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/696659
Conductive dome probes for measuring system level multi-GHZ signals Apr 3, 2007 Issued
Array ( [id] => 321660 [patent_doc_number] => 07523428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Hierarchical signal integrity analysis using interface logic models' [patent_app_type] => utility [patent_app_number] => 11/696149 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5634 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523428.pdf [firstpage_image] =>[orig_patent_app_number] => 11696149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/696149
Hierarchical signal integrity analysis using interface logic models Apr 2, 2007 Issued
Array ( [id] => 4722840 [patent_doc_number] => 20080244472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION' [patent_app_type] => utility [patent_app_number] => 11/692949 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2826 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244472.pdf [firstpage_image] =>[orig_patent_app_number] => 11692949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692949
METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION Mar 28, 2007 Abandoned
Array ( [id] => 4728839 [patent_doc_number] => 20080208383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'STITCHED IC CHIP LAYOUT METHODS, SYSTEMS AND PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 11/678069 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20080208383.pdf [firstpage_image] =>[orig_patent_app_number] => 11678069 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678069
Stitched IC layout methods, systems and program product Feb 22, 2007 Issued
Array ( [id] => 7972379 [patent_doc_number] => 07941768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Photolithographic process simulation in integrated circuit design and manufacturing' [patent_app_type] => utility [patent_app_number] => 11/708299 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 10394 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941768.pdf [firstpage_image] =>[orig_patent_app_number] => 11708299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708299
Photolithographic process simulation in integrated circuit design and manufacturing Feb 19, 2007 Issued
Array ( [id] => 860604 [patent_doc_number] => 07376928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure' [patent_app_type] => utility [patent_app_number] => 11/705448 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 52 [patent_no_of_words] => 5811 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376928.pdf [firstpage_image] =>[orig_patent_app_number] => 11705448 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705448
Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure Feb 12, 2007 Issued
Array ( [id] => 58928 [patent_doc_number] => 07770141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Computer recording medium for storing program of checking design rule of layout' [patent_app_type] => utility [patent_app_number] => 11/699669 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 10 [patent_no_of_words] => 6306 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/770/07770141.pdf [firstpage_image] =>[orig_patent_app_number] => 11699669 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699669
Computer recording medium for storing program of checking design rule of layout Jan 28, 2007 Issued
Array ( [id] => 5179352 [patent_doc_number] => 20070180412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole' [patent_app_type] => utility [patent_app_number] => 11/698029 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180412.pdf [firstpage_image] =>[orig_patent_app_number] => 11698029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698029
Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole Jan 25, 2007 Issued
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