
Sun J. Lin
Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 1569 |
| Issued Applications | 1454 |
| Pending Applications | 15 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 38584
[patent_doc_number] => 07788619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-31
[patent_title] => 'Memories, memory compiling systems and methods for the same'
[patent_app_type] => utility
[patent_app_number] => 11/819389
[patent_app_country] => US
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[pdf_file] => patents/07/788/07788619.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/819389 | Memories, memory compiling systems and methods for the same | Jun 26, 2007 | Issued |
Array
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[patent_doc_number] => 20080016483
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[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'HIERARCHICAL ANALOG LAYOUT SYNTHESIS AND OPTIMIZATION FOR INTEGRATED CIRCUITS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/757349 | Hierarchical analog layout synthesis and optimization for integrated circuits | Jun 1, 2007 | Issued |
Array
(
[id] => 268646
[patent_doc_number] => 07568175
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[patent_issue_date] => 2009-07-28
[patent_title] => 'Ramptime propagation on designs with cycles'
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[patent_app_number] => 11/757229
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/757229 | Ramptime propagation on designs with cycles | May 31, 2007 | Issued |
Array
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[patent_doc_number] => 20080086713
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-10
[patent_title] => 'METHOD AND APPARATUS FOR AUTOMATIC SYNTHESIS OF AN ELECTRONIC CIRCUIT MODEL'
[patent_app_type] => utility
[patent_app_number] => 11/756129
[patent_app_country] => US
[patent_app_date] => 2007-05-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11756129
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/756129 | Method and apparatus for automatic synthesis of an electronic circuit model | May 30, 2007 | Issued |
Array
(
[id] => 58368
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[patent_title] => 'Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device'
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[patent_app_number] => 11/755269
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/755269 | Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device | May 29, 2007 | Issued |
Array
(
[id] => 5577323
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[patent_title] => 'DOUBLE-LAYER INTEGRAL USING A STATIC GREEN\'S FUNCTION AND RECTANGULAR BASIS'
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[patent_app_number] => 11/754539
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754539 | DOUBLE-LAYER INTEGRAL USING A STATIC GREEN'S FUNCTION AND RECTANGULAR BASIS | May 28, 2007 | Abandoned |
Array
(
[id] => 4665590
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[patent_issue_date] => 2008-10-16
[patent_title] => 'Scan compression circuit and method of design therefor'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11807119
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/807119 | Scan compression circuit and method of design therefor | May 24, 2007 | Issued |
Array
(
[id] => 66673
[patent_doc_number] => 07765498
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-07-27
[patent_title] => 'Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist'
[patent_app_type] => utility
[patent_app_number] => 11/805739
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/805739 | Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist | May 23, 2007 | Issued |
Array
(
[id] => 816708
[patent_doc_number] => 07415695
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[patent_issue_date] => 2008-08-19
[patent_title] => 'System for search and analysis of systematic defects in integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/748575
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[patent_app_date] => 2007-05-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/748575 | System for search and analysis of systematic defects in integrated circuits | May 14, 2007 | Issued |
Array
(
[id] => 17608
[patent_doc_number] => 07805692
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-28
[patent_title] => 'Method for local hot spot fixing'
[patent_app_type] => utility
[patent_app_number] => 11/748599
[patent_app_country] => US
[patent_app_date] => 2007-05-15
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/748599 | Method for local hot spot fixing | May 14, 2007 | Issued |
Array
(
[id] => 108157
[patent_doc_number] => 07725857
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[patent_issue_date] => 2010-05-25
[patent_title] => 'Method for optimizing organizational floor layout and operations'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11737309
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/737309 | Method for optimizing organizational floor layout and operations | Apr 18, 2007 | Issued |
Array
(
[id] => 4684152
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[patent_issue_date] => 2008-10-09
[patent_title] => 'CIRCUIT EMULATION AND DEBUGGING METHOD'
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Array
(
[id] => 4684151
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[patent_title] => 'CONDUCTIVE DOME PROBES FOR MEASURING SYSTEM LEVEL MULTI-GHZ SIGNALS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/696659 | Conductive dome probes for measuring system level multi-GHZ signals | Apr 3, 2007 | Issued |
Array
(
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[patent_title] => 'Hierarchical signal integrity analysis using interface logic models'
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Array
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[id] => 4722840
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/692949 | METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION | Mar 28, 2007 | Abandoned |
Array
(
[id] => 4728839
[patent_doc_number] => 20080208383
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[patent_issue_date] => 2008-08-28
[patent_title] => 'STITCHED IC CHIP LAYOUT METHODS, SYSTEMS AND PROGRAM PRODUCT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/678069 | Stitched IC layout methods, systems and program product | Feb 22, 2007 | Issued |
Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/698029 | Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole | Jan 25, 2007 | Issued |