
Sun Jae Yoo
Examiner (ID: 5581, Phone: (571)272-9074 , Office: P/1626 )
| Most Active Art Unit | 1626 |
| Art Unit(s) | 1626, 1621, 1609, 1622 |
| Total Applications | 1919 |
| Issued Applications | 1171 |
| Pending Applications | 215 |
| Abandoned Applications | 564 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19452827
[patent_doc_number] => 20240312957
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => INTEGRATED VOLTAGE REGULATOR AND PASSIVE COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 18/399504
[patent_app_country] => US
[patent_app_date] => 2023-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11921
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399504
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/399504 | Integrated voltage regulator and passive components | Dec 27, 2023 | Issued |
Array
(
[id] => 20118426
[patent_doc_number] => 12368145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Display apparatus and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/543133
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 47
[patent_no_of_words] => 9907
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543133
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/543133 | Display apparatus and manufacturing method thereof | Dec 17, 2023 | Issued |
Array
(
[id] => 20066046
[patent_doc_number] => 20250204268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => CONCAVE TRAY BOTTOM ELECTRODE FOR MRAM
[patent_app_type] => utility
[patent_app_number] => 18/539532
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2247
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539532
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539532 | CONCAVE TRAY BOTTOM ELECTRODE FOR MRAM | Dec 13, 2023 | Pending |
Array
(
[id] => 20063336
[patent_doc_number] => 20250201558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => METHODS OF MANUFACTURING LOGIC DEVICES AND MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/539493
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2014
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539493
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539493 | METHODS OF MANUFACTURING LOGIC DEVICES AND MEMORY DEVICES | Dec 13, 2023 | Pending |
Array
(
[id] => 20162980
[patent_doc_number] => 12389637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => Nonvolatile semiconductor memory device including a memory cell
[patent_app_type] => utility
[patent_app_number] => 18/537954
[patent_app_country] => US
[patent_app_date] => 2023-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 60
[patent_figures_cnt] => 174
[patent_no_of_words] => 10223
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537954
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/537954 | Nonvolatile semiconductor memory device including a memory cell | Dec 12, 2023 | Issued |
Array
(
[id] => 19101181
[patent_doc_number] => 20240120409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => METHOD FOR NON-RESIST NANOLITHOGRAPHY
[patent_app_type] => utility
[patent_app_number] => 18/525131
[patent_app_country] => US
[patent_app_date] => 2023-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6264
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525131
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/525131 | Method for non-resist nanolithography | Nov 29, 2023 | Issued |
Array
(
[id] => 19071195
[patent_doc_number] => 20240105621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => DIE INTERCONNECT SUBSTRATE, AN ELECTRICAL DEVICE AND A METHOD FOR FORMING A DIE INTERCONNECT SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/525435
[patent_app_country] => US
[patent_app_date] => 2023-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14813
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525435
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/525435 | Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate | Nov 29, 2023 | Issued |
Array
(
[id] => 19054960
[patent_doc_number] => 20240096929
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING METAL INSULATOR METAL CAPACITOR
[patent_app_type] => utility
[patent_app_number] => 18/522752
[patent_app_country] => US
[patent_app_date] => 2023-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4061
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522752
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/522752 | Method of making semiconductor device including metal insulator metal capacitor | Nov 28, 2023 | Issued |
Array
(
[id] => 19517825
[patent_doc_number] => 20240349511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/521629
[patent_app_country] => US
[patent_app_date] => 2023-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16652
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521629
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/521629 | CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME | Nov 27, 2023 | Pending |
Array
(
[id] => 19900222
[patent_doc_number] => 12278158
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => Leadframe spacer for double-sided power module
[patent_app_type] => utility
[patent_app_number] => 18/520361
[patent_app_country] => US
[patent_app_date] => 2023-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520361
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/520361 | Leadframe spacer for double-sided power module | Nov 26, 2023 | Issued |
Array
(
[id] => 19783268
[patent_doc_number] => 12232323
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Three-dimensional semiconductor memory devices
[patent_app_type] => utility
[patent_app_number] => 18/515536
[patent_app_country] => US
[patent_app_date] => 2023-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 13537
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 274
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515536
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/515536 | Three-dimensional semiconductor memory devices | Nov 20, 2023 | Issued |
Array
(
[id] => 19781528
[patent_doc_number] => 12230566
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Metal-insulator-metal structure
[patent_app_type] => utility
[patent_app_number] => 18/511438
[patent_app_country] => US
[patent_app_date] => 2023-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8520
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511438
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/511438 | Metal-insulator-metal structure | Nov 15, 2023 | Issued |
Array
(
[id] => 19679454
[patent_doc_number] => 12191327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => CMOS image sensor having indented photodiode structure
[patent_app_type] => utility
[patent_app_number] => 18/500357
[patent_app_country] => US
[patent_app_date] => 2023-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 6069
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500357
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/500357 | CMOS image sensor having indented photodiode structure | Nov 1, 2023 | Issued |
Array
(
[id] => 18975226
[patent_doc_number] => 20240055318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => WIRE BONDED AIR HEAT SINK
[patent_app_type] => utility
[patent_app_number] => 18/493194
[patent_app_country] => US
[patent_app_date] => 2023-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493194
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/493194 | Wire bonded air heat sink | Oct 23, 2023 | Issued |
Array
(
[id] => 19634559
[patent_doc_number] => 20240413008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/382199
[patent_app_country] => US
[patent_app_date] => 2023-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11880
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18382199
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/382199 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME | Oct 19, 2023 | Pending |
Array
(
[id] => 18959164
[patent_doc_number] => 20240047491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => SENSOR PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/484407
[patent_app_country] => US
[patent_app_date] => 2023-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4936
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484407
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/484407 | SENSOR PACKAGE STRUCTURE | Oct 9, 2023 | Pending |
Array
(
[id] => 19893318
[patent_doc_number] => 20250118630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => DUAL SIDE STACKED TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 18/377672
[patent_app_country] => US
[patent_app_date] => 2023-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13557
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377672
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/377672 | DUAL SIDE STACKED TRANSISTOR | Oct 5, 2023 | Pending |
Array
(
[id] => 19679353
[patent_doc_number] => 12191225
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Ball grid array package design
[patent_app_type] => utility
[patent_app_number] => 18/375750
[patent_app_country] => US
[patent_app_date] => 2023-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4123
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375750
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/375750 | Ball grid array package design | Oct 1, 2023 | Issued |
Array
(
[id] => 19654470
[patent_doc_number] => 12176270
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Package structure with photonic die and method
[patent_app_type] => utility
[patent_app_number] => 18/472227
[patent_app_country] => US
[patent_app_date] => 2023-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 8413
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472227
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/472227 | Package structure with photonic die and method | Sep 21, 2023 | Issued |
Array
(
[id] => 19639624
[patent_doc_number] => 12170239
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-17
[patent_title] => Direct bonded copper substrates fabricated using silver sintering
[patent_app_type] => utility
[patent_app_number] => 18/469615
[patent_app_country] => US
[patent_app_date] => 2023-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3790
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469615
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/469615 | Direct bonded copper substrates fabricated using silver sintering | Sep 18, 2023 | Issued |