Search

Sun Jae Yoo

Examiner (ID: 5581, Phone: (571)272-9074 , Office: P/1626 )

Most Active Art Unit
1626
Art Unit(s)
1626, 1621, 1609, 1622
Total Applications
1919
Issued Applications
1171
Pending Applications
215
Abandoned Applications
564

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18927088 [patent_doc_number] => 20240030092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => RADIO FREQUENCY DEVICES INCLUDING RADIO FREQUENCY ABSORBENT FEATURES [patent_app_type] => utility [patent_app_number] => 18/351284 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351284
RADIO FREQUENCY DEVICES INCLUDING RADIO FREQUENCY ABSORBENT FEATURES Jul 11, 2023 Pending
Array ( [id] => 19452710 [patent_doc_number] => 20240312840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => THROUGH VIA STRUCTURE AND METHOD OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/349325 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349325
THROUGH VIA STRUCTURE AND METHOD OF FABRICATION THEREOF Jul 9, 2023 Pending
Array ( [id] => 18848769 [patent_doc_number] => 20230411173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE HAVING METAL THERMAL INTERFACE MATERIAL [patent_app_type] => utility [patent_app_number] => 18/349292 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349292 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349292
Semiconductor device package having metal thermal interface material Jul 9, 2023 Issued
Array ( [id] => 19484028 [patent_doc_number] => 20240332070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => ETCH STOP LAYER FOR INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/349672 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349672
ETCH STOP LAYER FOR INTERCONNECT STRUCTURES Jul 9, 2023 Pending
Array ( [id] => 19696398 [patent_doc_number] => 20250014943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => Surface Profile Control Of Passivation Layers In Integrated Circuit Chips [patent_app_type] => utility [patent_app_number] => 18/219259 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219259
Surface Profile Control Of Passivation Layers In Integrated Circuit Chips Jul 6, 2023 Pending
Array ( [id] => 19191560 [patent_doc_number] => 20240170473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/347594 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347594
CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Jul 5, 2023 Pending
Array ( [id] => 19401222 [patent_doc_number] => 12075634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => RRAM memory cell with multiple filaments [patent_app_type] => utility [patent_app_number] => 18/347794 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 9324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347794
RRAM memory cell with multiple filaments Jul 5, 2023 Issued
Array ( [id] => 18743376 [patent_doc_number] => 20230352364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INSULATING SUBSTRATE AND DUAL-SIDE COOLED POWER MODULE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/348049 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348049
Insulating substrate and power module using the same Jul 5, 2023 Issued
Array ( [id] => 18898614 [patent_doc_number] => 20240014099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE [patent_app_type] => utility [patent_app_number] => 18/348041 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348041
INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE Jul 5, 2023 Pending
Array ( [id] => 19696499 [patent_doc_number] => 20250015044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => DIE-SUBSTRATE INTERFACE INCLUDING LOCKING FEATURES [patent_app_type] => utility [patent_app_number] => 18/346976 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346976
DIE-SUBSTRATE INTERFACE INCLUDING LOCKING FEATURES Jul 4, 2023 Pending
Array ( [id] => 19221587 [patent_doc_number] => 20240186291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SEMICONDUCTOR DIE STACK STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/346674 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346674
SEMICONDUCTOR DIE STACK STRUCTURE Jul 2, 2023 Pending
Array ( [id] => 19494252 [patent_doc_number] => 12112975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Mechanism for finFET well doping [patent_app_type] => utility [patent_app_number] => 18/346622 [patent_app_country] => US [patent_app_date] => 2023-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 8319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346622
Mechanism for finFET well doping Jul 2, 2023 Issued
Array ( [id] => 19662062 [patent_doc_number] => 20240429127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => STRUCTURE WITH CAVITY AROUND THROUGH SEMICONDUCTOR VIA [patent_app_type] => utility [patent_app_number] => 18/340174 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340174
STRUCTURE WITH CAVITY AROUND THROUGH SEMICONDUCTOR VIA Jun 22, 2023 Pending
Array ( [id] => 19662075 [patent_doc_number] => 20240429140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SEMICONDUCTOR PACKAGE HAVING MULTIPLE REDISTRIBUTION LAYERS AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/213170 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213170
SEMICONDUCTOR PACKAGE HAVING MULTIPLE REDISTRIBUTION LAYERS AND METHOD OF MAKING THE SAME Jun 21, 2023 Pending
Array ( [id] => 19662119 [patent_doc_number] => 20240429184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => DIELECTRIC WAVEGUIDE FOR TRANSMITTING ELECTRICAL SIGNAL AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/338381 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338381
DIELECTRIC WAVEGUIDE FOR TRANSMITTING ELECTRICAL SIGNAL AND METHOD OF FORMING THE SAME Jun 20, 2023 Pending
Array ( [id] => 20638087 [patent_doc_number] => 12598986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Metal insulator metal capacitor (MIM capacitor) [patent_app_type] => utility [patent_app_number] => 18/337069 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337069
Metal insulator metal capacitor (MIM capacitor) Jun 18, 2023 Issued
Array ( [id] => 19646524 [patent_doc_number] => 20240421044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => Die-Attach Fillet Height Reduction [patent_app_type] => utility [patent_app_number] => 18/336376 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336376 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336376
Die-Attach Fillet Height Reduction Jun 15, 2023 Pending
Array ( [id] => 19646509 [patent_doc_number] => 20240421029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => Semiconductor Package [patent_app_type] => utility [patent_app_number] => 18/336358 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336358
Semiconductor Package Jun 15, 2023 Pending
Array ( [id] => 19646554 [patent_doc_number] => 20240421074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => THIN FILM RESISTOR, THERMISTOR AND METHOD OF PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 18/336412 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336412
THIN FILM RESISTOR, THERMISTOR AND METHOD OF PRODUCING THE SAME Jun 15, 2023 Issued
Array ( [id] => 19639622 [patent_doc_number] => 12170237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/334381 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 11647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334381
Semiconductor structure and manufacturing method thereof Jun 13, 2023 Issued
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