Search

Sun Mi Kim King

Examiner (ID: 9353, Phone: (571)270-1431 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
585
Issued Applications
388
Pending Applications
51
Abandoned Applications
172

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11132557 [patent_doc_number] => 20160329531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/214989 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 28719 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15214989 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/214989
Method for manufacturing semiconductor device Jul 19, 2016 Issued
Array ( [id] => 13709515 [patent_doc_number] => 20170365712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS [patent_app_type] => utility [patent_app_number] => 15/182906 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182906 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182906
Precise junction placement in vertical semiconductor devices using etch stop layers Jun 14, 2016 Issued
Array ( [id] => 13057465 [patent_doc_number] => 10050134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Methods for fabricating anode shorted field stop insulated gate bipolar transistor [patent_app_type] => utility [patent_app_number] => 15/177191 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 4865 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15177191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/177191
Methods for fabricating anode shorted field stop insulated gate bipolar transistor Jun 7, 2016 Issued
Array ( [id] => 12062058 [patent_doc_number] => 20170338402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'NOBLE METAL CAP LAYER FOR A METAL OXIDE CAP OF A MAGNETIC TUNNEL JUNCTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/157795 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157795 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/157795
NOBLE METAL CAP LAYER FOR A METAL OXIDE CAP OF A MAGNETIC TUNNEL JUNCTION STRUCTURE May 17, 2016 Abandoned
Array ( [id] => 16944276 [patent_doc_number] => 11056527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Metal oxide interface passivation for photon counting devices [patent_app_type] => utility [patent_app_number] => 15/145825 [patent_app_country] => US [patent_app_date] => 2016-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3216 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/145825
Metal oxide interface passivation for photon counting devices May 3, 2016 Issued
Array ( [id] => 12033855 [patent_doc_number] => 20170323954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/145804 [patent_app_country] => US [patent_app_date] => 2016-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145804 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/145804
Fin-type field effect transistor structure and manufacturing method thereof May 3, 2016 Issued
Array ( [id] => 11353903 [patent_doc_number] => 20160372642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/145972 [patent_app_country] => US [patent_app_date] => 2016-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 17698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15145972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/145972
Light emitting diode package and method of manufacturing the same May 3, 2016 Issued
Array ( [id] => 11050838 [patent_doc_number] => 20160247797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'LAYOUT STRUCTURE OF HETEROJUNCTION BIPOLAR TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/142948 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4461 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15142948 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/142948
LAYOUT STRUCTURE OF HETEROJUNCTION BIPOLAR TRANSISTORS Apr 28, 2016 Abandoned
Array ( [id] => 13832387 [patent_doc_number] => 20190019678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => DEVICE AND METHOD FOR BONDING OF SUBSTRATES [patent_app_type] => utility [patent_app_number] => 16/080156 [patent_app_country] => US [patent_app_date] => 2016-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16080156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/080156
Device and method for bonding of substrates Mar 21, 2016 Issued
Array ( [id] => 11032731 [patent_doc_number] => 20160229687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'CHIP PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/008371 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5626 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008371 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008371
CHIP PACKAGE AND FABRICATION METHOD THEREOF Jan 26, 2016 Abandoned
Array ( [id] => 11710545 [patent_doc_number] => 20170179044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/008432 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2864 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008432
Integrated circuit Jan 26, 2016 Issued
Array ( [id] => 10809642 [patent_doc_number] => 20160155801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'METHOD OF FORMING STRAINED STRUCTURES OF SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 15/005628 [patent_app_country] => US [patent_app_date] => 2016-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15005628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/005628
Method of forming strained structures of semiconductor devices Jan 24, 2016 Issued
Array ( [id] => 11466856 [patent_doc_number] => 09583497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Metal trench capacitor and improved isolation and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 15/000563 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6799 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15000563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/000563
Metal trench capacitor and improved isolation and methods of manufacture Jan 18, 2016 Issued
Array ( [id] => 12175052 [patent_doc_number] => 09893200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/972964 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 8733 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972964 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972964
Semiconductor device and method for manufacturing the same Dec 16, 2015 Issued
Array ( [id] => 10740748 [patent_doc_number] => 20160086899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'ROOM TEMPERATURE METAL DIRECT BONDING' [patent_app_type] => utility [patent_app_number] => 14/959204 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9166 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959204 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/959204
Room temperature metal direct bonding Dec 3, 2015 Issued
Array ( [id] => 11925777 [patent_doc_number] => 09793367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Ohmic contact to semiconductor' [patent_app_type] => utility [patent_app_number] => 14/955504 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5164 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/955504
Ohmic contact to semiconductor Nov 30, 2015 Issued
Array ( [id] => 13640733 [patent_doc_number] => 09847327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Switched-capacitor DC-to-DC converters [patent_app_type] => utility [patent_app_number] => 14/878748 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4129 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878748 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878748
Switched-capacitor DC-to-DC converters Oct 7, 2015 Issued
Array ( [id] => 10758461 [patent_doc_number] => 20160104614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'Semiconductor Device and a Method of Manufacturing Same' [patent_app_type] => utility [patent_app_number] => 14/878711 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4754 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878711
Semiconductor Device and a Method of Manufacturing Same Oct 7, 2015 Abandoned
Array ( [id] => 11475800 [patent_doc_number] => 20170062583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'METHODS AND SYSTEMS FOR REDUCING DISLOCATION DEFECTS IN HIGH CONCENTRATION EPITAXY PROCESSES' [patent_app_type] => utility [patent_app_number] => 14/879057 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879057 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/879057
Methods and systems for reducing dislocation defects in high concentration epitaxy processes Oct 7, 2015 Issued
Array ( [id] => 11502998 [patent_doc_number] => 20170077184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY CONTAINING SELF-ALIGNED MEMORY ELEMENTS' [patent_app_type] => utility [patent_app_number] => 14/851296 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851296 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851296
Three-dimensional resistive random access memory containing self-aligned memory elements Sep 10, 2015 Issued
Menu