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Sung Il Cho

Examiner (ID: 13560, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
629
Issued Applications
517
Pending Applications
85
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17948972 [patent_doc_number] => 20220335991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 17/469559 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469559 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469559
SEMICONDUCTOR APPARATUS Sep 7, 2021 Abandoned
Array ( [id] => 18238175 [patent_doc_number] => 20230070486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => TECHNOLOGIES FOR MAGNETIC-TUNNEL-JUNCTION-BASED RANDOM NUMBER GENERATION [patent_app_type] => utility [patent_app_number] => 17/467124 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467124
TECHNOLOGIES FOR MAGNETIC-TUNNEL-JUNCTION-BASED RANDOM NUMBER GENERATION Sep 2, 2021 Pending
Array ( [id] => 18857027 [patent_doc_number] => 11854618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Apparatuses, systems, and methods for determining extremum numerical values [patent_app_type] => utility [patent_app_number] => 17/446710 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446710
Apparatuses, systems, and methods for determining extremum numerical values Aug 31, 2021 Issued
Array ( [id] => 18983316 [patent_doc_number] => 11908501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Storage device that read data while a switching element of a memory cell is on [patent_app_type] => utility [patent_app_number] => 17/462449 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462449
Storage device that read data while a switching element of a memory cell is on Aug 30, 2021 Issued
Array ( [id] => 18227810 [patent_doc_number] => 20230066804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => COMPACT LOW-LEAKAGE MULTI-BIT COMPARE CAM CELL [patent_app_type] => utility [patent_app_number] => 17/462432 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462432
Compact low-leakage multi-bit compare CAM cell Aug 30, 2021 Issued
Array ( [id] => 18623555 [patent_doc_number] => 11756608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Write assist cell for static random access memory [patent_app_type] => utility [patent_app_number] => 17/460070 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460070
Write assist cell for static random access memory Aug 26, 2021 Issued
Array ( [id] => 18227247 [patent_doc_number] => 20230066241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Memory with Reduced Capacitance at a Sense Amplifier [patent_app_type] => utility [patent_app_number] => 17/446195 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446195
Memory with reduced capacitance at a sense amplifier Aug 26, 2021 Issued
Array ( [id] => 17660445 [patent_doc_number] => 20220180910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MEMORY BIT CELL CIRCUIT INCLUDING A BIT LINE COUPLED TO A STATIC RANDOM-ACCESS MEMORY (SRAM) BIT CELL CIRCUIT AND A NON-VOLATILE MEMORY (NVM) BIT CELL CIRCUIT AND A MEMORY BIT CELL ARRAY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/459186 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459186
Memory bit cell circuit including a bit line coupled to a static random-access memory (SRAM) bit cell circuit and a non-volatile memory (NVM) bit cell circuit and a memory bit cell array circuit Aug 26, 2021 Issued
Array ( [id] => 19679056 [patent_doc_number] => 12190927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory device with a bias circuit [patent_app_type] => utility [patent_app_number] => 17/407875 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407875 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407875
Memory device with a bias circuit Aug 19, 2021 Issued
Array ( [id] => 20111243 [patent_doc_number] => 12361978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Transmitting data signals on separate layers of a memory module, and related methods and apparatuses [patent_app_type] => utility [patent_app_number] => 17/443673 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443673
Transmitting data signals on separate layers of a memory module, and related methods and apparatuses Jul 26, 2021 Issued
Array ( [id] => 18149757 [patent_doc_number] => 20230023614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => CURRENT LEAKAGE MANAGEMENT CONTROLLER FOR READING FROM MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/385313 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385313
Current leakage management controller for reading from memory cells Jul 25, 2021 Issued
Array ( [id] => 17217502 [patent_doc_number] => 20210350840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/380899 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380899
SEMICONDUCTOR DEVICES Jul 19, 2021 Pending
Array ( [id] => 18112647 [patent_doc_number] => 20230005527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => MEMORY SYSTEMS INCLUDING MEMORY ARRAYS EMPLOYING COLUMN READ CIRCUITS TO CONTROL FLOATING OF COLUMN READ BIT LINES, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/364487 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364487
Memory systems including memory arrays employing column read circuits to control floating of column read bit lines, and related methods Jun 29, 2021 Issued
Array ( [id] => 18097036 [patent_doc_number] => 20220415377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => DUAL READ PORT LATCH ARRAY BITCELL [patent_app_type] => utility [patent_app_number] => 17/359445 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359445
Dual read port latch array bitcell Jun 24, 2021 Issued
Array ( [id] => 18097037 [patent_doc_number] => 20220415378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SPLIT READ PORT LATCH ARRAY BIT CELL [patent_app_type] => utility [patent_app_number] => 17/359446 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359446
Split read port latch array bit cell Jun 24, 2021 Issued
Array ( [id] => 18097045 [patent_doc_number] => 20220415386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => WEAK PRECHARGE BEFORE WRITE DUAL-RAIL SRAM WRITE OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 17/358527 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358527 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358527
Weak precharge before write dual-rail SRAM write optimization Jun 24, 2021 Issued
Array ( [id] => 17115287 [patent_doc_number] => 20210295884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => NONVOLATILE MEMORY DEVICES INCLUDING MEMORY PLANES AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/338097 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338097
Nonvolatile memory devices including memory planes and memory systems including the same Jun 2, 2021 Issued
Array ( [id] => 18304247 [patent_doc_number] => 11626159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Computing in-memory device supporting arithmetic operations and method of controlling the same [patent_app_type] => utility [patent_app_number] => 17/336451 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4173 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336451
Computing in-memory device supporting arithmetic operations and method of controlling the same Jun 1, 2021 Issued
Array ( [id] => 18039728 [patent_doc_number] => 20220383945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY SYSTEM WITH BURST MODE HAVING LOGIC GATES AS SENSE ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/333691 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333691
Memory system with burst mode having logic gates as sense elements May 27, 2021 Issued
Array ( [id] => 17566304 [patent_doc_number] => 20220130453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => STATIC RANDOM ACCESS MEMORY (SRAM) DEVICES AND METHODS OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/332004 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332004
Static random access memory (SRAM) devices and methods of operating the same May 26, 2021 Issued
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