
Sung Il Cho
Examiner (ID: 13560, Phone: (571)270-0137 , Office: P/2825 )
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825 |
| Total Applications | 629 |
| Issued Applications | 517 |
| Pending Applications | 85 |
| Abandoned Applications | 50 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19414507
[patent_doc_number] => 12080341
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-03
[patent_title] => Memory device including dual control circuits
[patent_app_type] => utility
[patent_app_number] => 17/141124
[patent_app_country] => US
[patent_app_date] => 2021-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8088
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 310
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141124
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/141124 | Memory device including dual control circuits | Jan 3, 2021 | Issued |
Array
(
[id] => 16752497
[patent_doc_number] => 20210104509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => MEMORY CELL ARRAY AND METHOD OF OPERATING SAME
[patent_app_type] => utility
[patent_app_number] => 17/122652
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15496
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122652
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/122652 | Memory circuit and method of operating same | Dec 14, 2020 | Issued |
Array
(
[id] => 16811816
[patent_doc_number] => 20210134371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => SRAM MEMORY HAVING SUBARRAYS WITH COMMON IO BLOCK
[patent_app_type] => utility
[patent_app_number] => 17/120702
[patent_app_country] => US
[patent_app_date] => 2020-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4698
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120702
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/120702 | SRAM MEMORY HAVING SUBARRAYS WITH COMMON IO BLOCK | Dec 13, 2020 | Pending |
Array
(
[id] => 16782535
[patent_doc_number] => 20210119614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/113763
[patent_app_country] => US
[patent_app_date] => 2020-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 56330
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113763
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/113763 | Semiconductor device comprising a logic circuit and a holding unit | Dec 6, 2020 | Issued |
Array
(
[id] => 18131121
[patent_doc_number] => 11557336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Static random access memory with adaptive precharge signal generated in response to tracking operation
[patent_app_type] => utility
[patent_app_number] => 17/107165
[patent_app_country] => US
[patent_app_date] => 2020-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 17188
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107165
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/107165 | Static random access memory with adaptive precharge signal generated in response to tracking operation | Nov 29, 2020 | Issued |
Array
(
[id] => 16951437
[patent_doc_number] => 20210210129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => ACCESS SCHEMES FOR PROTECTING STORED DATA IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/103521
[patent_app_country] => US
[patent_app_date] => 2020-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 51130
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103521
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/103521 | Access schemes for protecting stored data in a memory device | Nov 23, 2020 | Issued |
Array
(
[id] => 18967227
[patent_doc_number] => 11901005
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-13
[patent_title] => Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells
[patent_app_type] => utility
[patent_app_number] => 16/953092
[patent_app_country] => US
[patent_app_date] => 2020-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 25
[patent_no_of_words] => 21722
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953092
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/953092 | Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells | Nov 18, 2020 | Issued |
Array
(
[id] => 17522895
[patent_doc_number] => 20220108744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-07
[patent_title] => BITLINE PRECHARGE SYSTEM FOR A SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/952712
[patent_app_country] => US
[patent_app_date] => 2020-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3064
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952712
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/952712 | Bitline precharge system for a semiconductor memory device | Nov 18, 2020 | Issued |
Array
(
[id] => 16677012
[patent_doc_number] => 20210065778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => COMPARISON OPERATIONS IN MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/098160
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33033
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098160
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/098160 | Comparison operations in memory | Nov 12, 2020 | Issued |
Array
(
[id] => 16660377
[patent_doc_number] => 20210057014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => CONTROL METHOD FOR MEMORY AND NON-TRANSITORY COMPUTER-READABLE MEDIA
[patent_app_type] => utility
[patent_app_number] => 17/094385
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4269
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094385
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094385 | Control method for memory and non-transitory computer-readable media | Nov 9, 2020 | Issued |
Array
(
[id] => 17772164
[patent_doc_number] => 11404115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-02
[patent_title] => Memory with write assist scheme
[patent_app_type] => utility
[patent_app_number] => 17/084635
[patent_app_country] => US
[patent_app_date] => 2020-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4824
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084635
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/084635 | Memory with write assist scheme | Oct 29, 2020 | Issued |
Array
(
[id] => 17318536
[patent_doc_number] => 20210407586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/082477
[patent_app_country] => US
[patent_app_date] => 2020-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7426
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082477
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/082477 | Memory device and operation method thereof | Oct 27, 2020 | Issued |
Array
(
[id] => 16936101
[patent_doc_number] => 20210201990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-01
[patent_title] => Memory Device
[patent_app_type] => utility
[patent_app_number] => 17/082404
[patent_app_country] => US
[patent_app_date] => 2020-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6511
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082404
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/082404 | Memory device having a negative voltage circuit | Oct 27, 2020 | Issued |
Array
(
[id] => 17551313
[patent_doc_number] => 20220122655
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => 3D STORAGE ARCHITECTURE WITH TIER-SPECIFIC CONTROLS
[patent_app_type] => utility
[patent_app_number] => 17/071449
[patent_app_country] => US
[patent_app_date] => 2020-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5930
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071449
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/071449 | 3D storage architecture with tier-specific controls | Oct 14, 2020 | Issued |
Array
(
[id] => 18857024
[patent_doc_number] => 11854615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Stored charge use in cross-point memory
[patent_app_type] => utility
[patent_app_number] => 17/065295
[patent_app_country] => US
[patent_app_date] => 2020-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3144
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065295
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/065295 | Stored charge use in cross-point memory | Oct 6, 2020 | Issued |
Array
(
[id] => 18009560
[patent_doc_number] => 20220368327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => CIRCUIT FOR MITIGATING SINGLE-EVENT-TRANSIENTS
[patent_app_type] => utility
[patent_app_number] => 17/767016
[patent_app_country] => US
[patent_app_date] => 2020-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13108
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17767016
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/767016 | Circuit for mitigating single-event-transients | Oct 6, 2020 | Issued |
Array
(
[id] => 18105321
[patent_doc_number] => 11545215
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-03
[patent_title] => Devices and methods for writing to a memory cell of a memory
[patent_app_type] => utility
[patent_app_number] => 17/030536
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5088
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030536
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/030536 | Devices and methods for writing to a memory cell of a memory | Sep 23, 2020 | Issued |
Array
(
[id] => 17485667
[patent_doc_number] => 20220093171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => PSEUDO-TRIPLE-PORT SRAM DATAPATHS
[patent_app_type] => utility
[patent_app_number] => 17/028965
[patent_app_country] => US
[patent_app_date] => 2020-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8790
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028965
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/028965 | Pseudo-triple-port SRAM datapaths | Sep 21, 2020 | Issued |
Array
(
[id] => 17516630
[patent_doc_number] => 11295789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-05
[patent_title] => Latching sense amplifier
[patent_app_type] => utility
[patent_app_number] => 17/027124
[patent_app_country] => US
[patent_app_date] => 2020-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4352
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027124
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/027124 | Latching sense amplifier | Sep 20, 2020 | Issued |
Array
(
[id] => 16723492
[patent_doc_number] => 20210090639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => ENHANCED READ SENSING MARGIN FOR SRAM CELL ARRAYS
[patent_app_type] => utility
[patent_app_number] => 17/025448
[patent_app_country] => US
[patent_app_date] => 2020-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9923
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025448
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/025448 | Enhanced read sensing margin for SRAM cell arrays | Sep 17, 2020 | Issued |