Search

Sung Il Cho

Examiner (ID: 10363, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
626
Issued Applications
511
Pending Applications
97
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16471406 [patent_doc_number] => 20200372944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => PARALLEL ACCESS TECHNIQUES WITHIN MEMORY SECTIONS THROUGH SECTION INDEPENDENCE [patent_app_type] => utility [patent_app_number] => 16/993675 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993675
Parallel access techniques within memory sections through section independence Aug 13, 2020 Issued
Array ( [id] => 17978410 [patent_doc_number] => 11495282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Sense amplifier drivers, and related devices, systems, and methods [patent_app_type] => utility [patent_app_number] => 16/991290 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 11254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991290
Sense amplifier drivers, and related devices, systems, and methods Aug 11, 2020 Issued
Array ( [id] => 17416805 [patent_doc_number] => 20220051709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => ROW-WISE TRACKING OF REFERENCE GENERATION FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/990441 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990441
ROW-WISE TRACKING OF REFERENCE GENERATION FOR MEMORY DEVICES Aug 10, 2020 Abandoned
Array ( [id] => 18639264 [patent_doc_number] => 11763880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Column multiplexer circuitry [patent_app_type] => utility [patent_app_number] => 16/990951 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7813 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990951
Column multiplexer circuitry Aug 10, 2020 Issued
Array ( [id] => 18304239 [patent_doc_number] => 11626151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Single plate configuration and memory array operation [patent_app_type] => utility [patent_app_number] => 16/983469 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16916 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983469 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983469
Single plate configuration and memory array operation Aug 2, 2020 Issued
Array ( [id] => 16440136 [patent_doc_number] => 20200357463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => CIRCUIT AND METHOD OF WRITING TO A BIT CELL [patent_app_type] => utility [patent_app_number] => 16/940315 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940315 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940315
Circuit and method of writing to a bit cell Jul 26, 2020 Issued
Array ( [id] => 17622960 [patent_doc_number] => 11342019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Compensation word line driver [patent_app_type] => utility [patent_app_number] => 16/937824 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937824
Compensation word line driver Jul 23, 2020 Issued
Array ( [id] => 18190429 [patent_doc_number] => 11581030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Resistive memory with adjustable write parameter [patent_app_type] => utility [patent_app_number] => 16/932984 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5112 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932984 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932984
Resistive memory with adjustable write parameter Jul 19, 2020 Issued
Array ( [id] => 17365811 [patent_doc_number] => 11232840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Semiconductor device including page buffer [patent_app_type] => utility [patent_app_number] => 16/932522 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8926 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932522 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932522
Semiconductor device including page buffer Jul 16, 2020 Issued
Array ( [id] => 16402069 [patent_doc_number] => 20200342927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => Highly reliable STT-MRAM structure and implementation method thereof [patent_app_type] => utility [patent_app_number] => 16/928716 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928716
Highly reliable STT-MRAM structure and implementation method thereof Jul 13, 2020 Issued
Array ( [id] => 16402089 [patent_doc_number] => 20200342947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => METHOD FOR PROGRAMMING A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/924133 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924133
Method for programming a memory system Jul 7, 2020 Issued
Array ( [id] => 18131120 [patent_doc_number] => 11557335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Erasing a partition of an SRAM array with hardware support [patent_app_type] => utility [patent_app_number] => 16/922370 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5784 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922370
Erasing a partition of an SRAM array with hardware support Jul 6, 2020 Issued
Array ( [id] => 16730910 [patent_doc_number] => 20210098058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => Embedded SRAM Write Assist Circuit [patent_app_type] => utility [patent_app_number] => 16/922270 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922270 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922270
Embedded SRAM write assist circuit Jul 6, 2020 Issued
Array ( [id] => 17318528 [patent_doc_number] => 20210407578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => LAYOUTS FOR SENSE AMPLIFIERS AND RELATED APPARATUSES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/917233 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917233
Layouts for sense amplifiers and related apparatuses and systems Jun 29, 2020 Issued
Array ( [id] => 17908414 [patent_doc_number] => 11462274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Semiconductor memory device reducing bit line precharge operation time and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/917499 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7236 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917499
Semiconductor memory device reducing bit line precharge operation time and method of operating the same Jun 29, 2020 Issued
Array ( [id] => 17757987 [patent_doc_number] => 11398285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Memory cell mis-shape mitigation [patent_app_type] => utility [patent_app_number] => 16/910504 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 19485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910504 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910504
Memory cell mis-shape mitigation Jun 23, 2020 Issued
Array ( [id] => 18105307 [patent_doc_number] => 11545201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Memory device with unipolar selector [patent_app_type] => utility [patent_app_number] => 16/908914 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 8824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908914 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908914
Memory device with unipolar selector Jun 22, 2020 Issued
Array ( [id] => 17493247 [patent_doc_number] => 11282557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Magnetic cache for a memory device [patent_app_type] => utility [patent_app_number] => 16/908420 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16059 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908420 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908420
Magnetic cache for a memory device Jun 21, 2020 Issued
Array ( [id] => 16723518 [patent_doc_number] => 20210090665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 16/906140 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906140
Semiconductor storage apparatus including a memory cell array Jun 18, 2020 Issued
Array ( [id] => 17893349 [patent_doc_number] => 11456333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof [patent_app_type] => utility [patent_app_number] => 16/903654 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 48 [patent_no_of_words] => 19822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903654
Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof Jun 16, 2020 Issued
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