Sung Il Cho

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Array ( [id] => 19483725 [patent_doc_number] => 20240331767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => BIT CELL BASED WRITE SELF-TIME DELAY PATH [patent_app_type] => utility [patent_app_number] => 18/614460 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20139189 [patent_doc_number] => 20250246233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => STORAGE CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/610381 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19285351 [patent_doc_number] => 20240221828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION [patent_app_type] => utility [patent_app_number] => 18/603118 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20118214 [patent_doc_number] => 12367929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Memory device having a negative voltage circuit [patent_app_type] => utility [patent_app_number] => 18/601706 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 1121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601706 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 20317962 [patent_doc_number] => 12456517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Semiconductor flash memory device with voltage control on completion of a program operation and subsequent to completion of the program operation [patent_app_type] => utility [patent_app_number] => 18/591563 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2590 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19252513 [patent_doc_number] => 20240203510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SFGT STORAGE ARRAY, STORAGE CHIP AND DATA-READING METHOD [patent_app_type] => utility [patent_app_number] => 18/588007 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588007 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 19452384 [patent_doc_number] => 20240312514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => NEGATIVE BIT LINE CONTROL MECHANISM [patent_app_type] => utility [patent_app_number] => 18/444754 [patent_app_country] => US [patent_app_date] => 2024-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20167637 [patent_doc_number] => 20250259684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => READ METHOD ENHANCEMENT TO REDUCE READ DISTURB IN MIXED-MODE MEMORY STORAGE REGIONS [patent_app_type] => utility [patent_app_number] => 18/437794 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20167624 [patent_doc_number] => 20250259671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => INCREASED THROUGHPUT FOR READS IN STATIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/436228 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436228 [rel_patent_id] =>[rel_patent_doc_number] =>)

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