Search

Sung Il Cho

Examiner (ID: 10363, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
626
Issued Applications
511
Pending Applications
97
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16811782 [patent_doc_number] => 20210134337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/491928 [patent_app_country] => US [patent_app_date] => 2018-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16491928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/491928
Control circuit, semiconductor memory device, information processing device, and control method Feb 13, 2018 Issued
Array ( [id] => 14827409 [patent_doc_number] => 10410715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Pre-charging bit lines through charge-sharing [patent_app_type] => utility [patent_app_number] => 15/896247 [patent_app_country] => US [patent_app_date] => 2018-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15896247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/896247
Pre-charging bit lines through charge-sharing Feb 13, 2018 Issued
Array ( [id] => 12800026 [patent_doc_number] => 20180158511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/887190 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887190 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887190
Semiconductor SRAM circuit having a plurality of MOSFETS controlling ground potential Feb 1, 2018 Issued
Array ( [id] => 15732885 [patent_doc_number] => 10614875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Logical operations using memory cells [patent_app_type] => utility [patent_app_number] => 15/884179 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8341 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884179
Logical operations using memory cells Jan 29, 2018 Issued
Array ( [id] => 13270819 [patent_doc_number] => 10147496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => OTPROM for post-process programming using selective breakdown [patent_app_type] => utility [patent_app_number] => 15/881356 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881356
OTPROM for post-process programming using selective breakdown Jan 25, 2018 Issued
Array ( [id] => 15092587 [patent_doc_number] => 20190341105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => METHOD FOR USING ELECTROCHEMICAL COMPONENTS FOR STORAGE OF ENERGY AND INFORMATION AND ASSOCIATED ELECTRONIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/475195 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475195 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/475195
Method for using electrochemical components for storage of energy and information and associated electronic circuit Dec 21, 2017 Issued
Array ( [id] => 15139003 [patent_doc_number] => 10482983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Read disturb detection based on dynamic bit error rate estimation [patent_app_type] => utility [patent_app_number] => 15/850273 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850273 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850273
Read disturb detection based on dynamic bit error rate estimation Dec 20, 2017 Issued
Array ( [id] => 16249211 [patent_doc_number] => 10748583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Dummy bitline circuitry [patent_app_type] => utility [patent_app_number] => 15/851341 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851341 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/851341
Dummy bitline circuitry Dec 20, 2017 Issued
Array ( [id] => 16279907 [patent_doc_number] => 10762944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Single plate configuration and memory array operation [patent_app_type] => utility [patent_app_number] => 15/845893 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16867 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845893 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845893
Single plate configuration and memory array operation Dec 17, 2017 Issued
Array ( [id] => 12871861 [patent_doc_number] => 20180182462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/844221 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844221
SEMICONDUCTOR STORAGE DEVICE Dec 14, 2017 Abandoned
Array ( [id] => 13613097 [patent_doc_number] => 20180358098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/844197 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844197 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844197
Storage device and operating method for applying a program voltage to erased word line to close open memory block Dec 14, 2017 Issued
Array ( [id] => 14475101 [patent_doc_number] => 20190189196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => STAGED BITLINE PRECHARGE [patent_app_type] => utility [patent_app_number] => 15/841649 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841649
Staged bitline precharge Dec 13, 2017 Issued
Array ( [id] => 14445857 [patent_doc_number] => 20190180802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => WAVE PIPELINE [patent_app_type] => utility [patent_app_number] => 15/834315 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/834315
Skew reduction of a wave pipeline in a memory device Dec 6, 2017 Issued
Array ( [id] => 15547159 [patent_doc_number] => 10573369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Semiconductor memory device performing a target refresh operation based on a target address signal [patent_app_type] => utility [patent_app_number] => 15/832063 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6063 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832063
Semiconductor memory device performing a target refresh operation based on a target address signal Dec 4, 2017 Issued
Array ( [id] => 14491619 [patent_doc_number] => 10332607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Methods of operating a nonvolatile memory device and the nonvolatile memory device thereof [patent_app_type] => utility [patent_app_number] => 15/830679 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 9495 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830679 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830679
Methods of operating a nonvolatile memory device and the nonvolatile memory device thereof Dec 3, 2017 Issued
Array ( [id] => 15169561 [patent_doc_number] => 10490283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Memory management method, memory control circuit unit and memory storage device [patent_app_type] => utility [patent_app_number] => 15/831319 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831319 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831319
Memory management method, memory control circuit unit and memory storage device Dec 3, 2017 Issued
Array ( [id] => 15286607 [patent_doc_number] => 10515973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Wordline bridge in a 3D memory array [patent_app_type] => utility [patent_app_number] => 15/828039 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8478 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828039 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/828039
Wordline bridge in a 3D memory array Nov 29, 2017 Issued
Array ( [id] => 14671527 [patent_doc_number] => 10373678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => SRAM margin recovery during burn-in [patent_app_type] => utility [patent_app_number] => 15/826990 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5458 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826990 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826990
SRAM margin recovery during burn-in Nov 29, 2017 Issued
Array ( [id] => 14737943 [patent_doc_number] => 10388380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Semiconductor device and memory circuit having an OS transistor and a capacitor [patent_app_type] => utility [patent_app_number] => 15/823662 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 46 [patent_no_of_words] => 26900 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823662
Semiconductor device and memory circuit having an OS transistor and a capacitor Nov 27, 2017 Issued
Array ( [id] => 12822889 [patent_doc_number] => 20180166135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => Resistive Random Access Memory Cell [patent_app_type] => utility [patent_app_number] => 15/823323 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823323 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823323
Resistive random access memory cell Nov 26, 2017 Issued
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