
Sung Il Cho
Examiner (ID: 10363, Phone: (571)270-0137 , Office: P/2825 )
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825 |
| Total Applications | 626 |
| Issued Applications | 511 |
| Pending Applications | 97 |
| Abandoned Applications | 50 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13030361
[patent_doc_number] => 10037803
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-31
[patent_title] => Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value
[patent_app_type] => utility
[patent_app_number] => 15/394207
[patent_app_country] => US
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Array
(
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[patent_doc_number] => 10332584
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[patent_kind] => B2
[patent_issue_date] => 2019-06-25
[patent_title] => Semiconductor device including subword driver circuit
[patent_app_type] => utility
[patent_app_number] => 15/382358
[patent_app_country] => US
[patent_app_date] => 2016-12-16
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Array
(
[id] => 11459788
[patent_doc_number] => 20170053693
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[patent_issue_date] => 2017-02-23
[patent_title] => 'COMPARISON OPERATIONS IN MEMORY'
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[patent_app_country] => US
[patent_app_date] => 2016-11-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/346526 | Comparison operations in memory | Nov 7, 2016 | Issued |
Array
(
[id] => 11446892
[patent_doc_number] => 20170047913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-16
[patent_title] => 'ELECTRONIC COMPARISON SYSTEMS'
[patent_app_type] => utility
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/334649 | Electronic comparison systems | Oct 25, 2016 | Issued |
Array
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[patent_issue_date] => 2017-04-20
[patent_title] => 'MEMORY DEVICE AND SYSTEM SUPPORTING COMMAND BUS TRAINING, AND OPERATING METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/298491 | Memory device and system supporting command bus training, and operating method thereof | Oct 19, 2016 | Issued |
Array
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[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/292548 | NAND structure with tier select gate transistors | Oct 12, 2016 | Issued |
Array
(
[id] => 12416325
[patent_doc_number] => 09972388
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[patent_issue_date] => 2018-05-15
[patent_title] => Method, system and device for power-up operation
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/291627 | Method, system and device for power-up operation | Oct 11, 2016 | Issued |
Array
(
[id] => 12497883
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[patent_issue_date] => 2018-06-12
[patent_title] => Non-volatile memory device with a plurality of cache latches and switches and method for operating non-volatile memory device
[patent_app_type] => utility
[patent_app_number] => 15/288918
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/288918 | Non-volatile memory device with a plurality of cache latches and switches and method for operating non-volatile memory device | Oct 6, 2016 | Issued |
Array
(
[id] => 11397761
[patent_doc_number] => 20170018298
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[patent_issue_date] => 2017-01-19
[patent_title] => 'LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/280935 | Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory | Sep 28, 2016 | Issued |
Array
(
[id] => 12935248
[patent_doc_number] => 09830968
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[patent_issue_date] => 2017-11-28
[patent_title] => Spin orbit torque (SOT) magnetic memory cell and array
[patent_app_type] => utility
[patent_app_number] => 15/266120
[patent_app_country] => US
[patent_app_date] => 2016-09-15
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Array
(
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[patent_title] => DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/265949 | Data storage device and operating method of determining appropriateness of a read bias | Sep 14, 2016 | Issued |
Array
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[patent_title] => 'Semiconductor memory device which applies multiple voltages to the word line'
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Array
(
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[patent_title] => 'Polyphase buffer for rate-conversion'
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Array
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[patent_title] => Random number generator by superparamagnetism
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/228559 | Ternary content addressable memories having a bit cell with memristors and serially connected match-line transistors | Aug 3, 2016 | Issued |
Array
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[patent_title] => Power supply management circuit configured to manage power transfer with limiting current intensity, and storage device and communication cable including the same
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/223827 | Power supply management circuit configured to manage power transfer with limiting current intensity, and storage device and communication cable including the same | Jul 28, 2016 | Issued |