Search

Sung Il Cho

Examiner (ID: 10363, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
626
Issued Applications
511
Pending Applications
97
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13030361 [patent_doc_number] => 10037803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value [patent_app_type] => utility [patent_app_number] => 15/394207 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5279 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394207 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394207
Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value Dec 28, 2016 Issued
Array ( [id] => 14491573 [patent_doc_number] => 10332584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Semiconductor device including subword driver circuit [patent_app_type] => utility [patent_app_number] => 15/382358 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7043 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382358 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382358
Semiconductor device including subword driver circuit Dec 15, 2016 Issued
Array ( [id] => 11459788 [patent_doc_number] => 20170053693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'COMPARISON OPERATIONS IN MEMORY' [patent_app_type] => utility [patent_app_number] => 15/346526 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 35395 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346526
Comparison operations in memory Nov 7, 2016 Issued
Array ( [id] => 11446892 [patent_doc_number] => 20170047913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'ELECTRONIC COMPARISON SYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/334649 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13534 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/334649
Electronic comparison systems Oct 25, 2016 Issued
Array ( [id] => 11571522 [patent_doc_number] => 20170110165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'MEMORY DEVICE AND SYSTEM SUPPORTING COMMAND BUS TRAINING, AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/298491 [patent_app_country] => US [patent_app_date] => 2016-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/298491
Memory device and system supporting command bus training, and operating method thereof Oct 19, 2016 Issued
Array ( [id] => 11983411 [patent_doc_number] => 20170287566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/292548 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292548 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/292548
NAND structure with tier select gate transistors Oct 12, 2016 Issued
Array ( [id] => 12416325 [patent_doc_number] => 09972388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Method, system and device for power-up operation [patent_app_type] => utility [patent_app_number] => 15/291627 [patent_app_country] => US [patent_app_date] => 2016-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8710 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15291627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/291627
Method, system and device for power-up operation Oct 11, 2016 Issued
Array ( [id] => 12497883 [patent_doc_number] => 09997250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Non-volatile memory device with a plurality of cache latches and switches and method for operating non-volatile memory device [patent_app_type] => utility [patent_app_number] => 15/288918 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7120 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288918 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/288918
Non-volatile memory device with a plurality of cache latches and switches and method for operating non-volatile memory device Oct 6, 2016 Issued
Array ( [id] => 11397761 [patent_doc_number] => 20170018298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/280935 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/280935
Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory Sep 28, 2016 Issued
Array ( [id] => 12935248 [patent_doc_number] => 09830968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Spin orbit torque (SOT) magnetic memory cell and array [patent_app_type] => utility [patent_app_number] => 15/266120 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 5899 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/266120
Spin orbit torque (SOT) magnetic memory cell and array Sep 14, 2016 Issued
Array ( [id] => 13708705 [patent_doc_number] => 20170365307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => DATA STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/265949 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265949 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/265949
Data storage device and operating method of determining appropriateness of a read bias Sep 14, 2016 Issued
Array ( [id] => 11925411 [patent_doc_number] => 09792996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-17 [patent_title] => 'Semiconductor memory device which applies multiple voltages to the word line' [patent_app_type] => utility [patent_app_number] => 15/265810 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 17101 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/265810
Semiconductor memory device which applies multiple voltages to the word line Sep 13, 2016 Issued
Array ( [id] => 11811342 [patent_doc_number] => 09715914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Polyphase buffer for rate-conversion' [patent_app_type] => utility [patent_app_number] => 15/259161 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9590 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259161
Polyphase buffer for rate-conversion Sep 7, 2016 Issued
Array ( [id] => 13767213 [patent_doc_number] => 10175948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Random number generator by superparamagnetism [patent_app_type] => utility [patent_app_number] => 15/257741 [patent_app_country] => US [patent_app_date] => 2016-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 8321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15257741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/257741
Random number generator by superparamagnetism Sep 5, 2016 Issued
Array ( [id] => 12208311 [patent_doc_number] => 20180053538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'APPARATUSES AND METHODS FOR ADJUSTING DELAY OF COMMAND SIGNAL PATH' [patent_app_type] => utility [patent_app_number] => 15/243651 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8475 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15243651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/243651
Apparatuses and methods for adjusting delay of command signal path Aug 21, 2016 Issued
Array ( [id] => 11911019 [patent_doc_number] => 09779837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Semiconductor test system during burn-in process' [patent_app_type] => utility [patent_app_number] => 15/240125 [patent_app_country] => US [patent_app_date] => 2016-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5227 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15240125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/240125
Semiconductor test system during burn-in process Aug 17, 2016 Issued
Array ( [id] => 11911012 [patent_doc_number] => 09779830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Non-volatile semiconductor memory device and erase method thereof' [patent_app_type] => utility [patent_app_number] => 15/233231 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233231 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233231
Non-volatile semiconductor memory device and erase method thereof Aug 9, 2016 Issued
Array ( [id] => 12181430 [patent_doc_number] => 20180040366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'PRE-CHARGING BIT LINES THROUGH CHARGE-SHARING' [patent_app_type] => utility [patent_app_number] => 15/231293 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/231293
Pre-charging bit lines through charge-sharing Aug 7, 2016 Issued
Array ( [id] => 12181439 [patent_doc_number] => 20180040374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'TERNARY CONTENT ADDRESSABLE MEMORIES HAVING A BIT CELL WITH MEMRISTORS AND SERIALLY CONNECTED MATCH-LINE TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/228559 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 19295 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228559 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228559
Ternary content addressable memories having a bit cell with memristors and serially connected match-line transistors Aug 3, 2016 Issued
Array ( [id] => 14426243 [patent_doc_number] => 10317922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Power supply management circuit configured to manage power transfer with limiting current intensity, and storage device and communication cable including the same [patent_app_type] => utility [patent_app_number] => 15/223827 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 12780 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15223827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/223827
Power supply management circuit configured to manage power transfer with limiting current intensity, and storage device and communication cable including the same Jul 28, 2016 Issued
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