Search

Sung Il Cho

Examiner (ID: 9242, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
653
Issued Applications
535
Pending Applications
76
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20102869 [patent_doc_number] => 20250232805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY CIRCUITS WITH TRACKING CELLS AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/630365 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630365
MEMORY CIRCUITS WITH TRACKING CELLS AND METHODS FOR OPERATING THE SAME Apr 8, 2024 Pending
Array ( [id] => 19335339 [patent_doc_number] => 20240249769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Reconfigurable Compute Memory Having Selection Logic to Control Compute Operations [patent_app_type] => utility [patent_app_number] => 18/626860 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626860
Reconfigurable Compute Memory Having Selection Logic to Control Compute Operations Apr 3, 2024 Pending
Array ( [id] => 19483726 [patent_doc_number] => 20240331768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM [patent_app_type] => utility [patent_app_number] => 18/619699 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619699 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619699
BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM Mar 27, 2024 Pending
Array ( [id] => 20283342 [patent_doc_number] => 20250308584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => FLEXIBLE SRAM CELL ASSIST BY COMBINING WL AND SELECTIVE SRAM CELL SUPPLY [patent_app_type] => utility [patent_app_number] => 18/617275 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617275
Flexible SRAM cell assist by combining WL and selective SRAM cell supply Mar 25, 2024 Issued
Array ( [id] => 20283341 [patent_doc_number] => 20250308583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => DELAY CIRCUITRY BASED ON PSEUDO-SRAM CELLS FOR CONTROLLING THE SRAM SENSE AMPLIFIER TIMING [patent_app_type] => utility [patent_app_number] => 18/617168 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617168 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617168
DELAY CIRCUITRY BASED ON PSEUDO-SRAM CELLS FOR CONTROLLING THE SRAM SENSE AMPLIFIER TIMING Mar 25, 2024 Pending
Array ( [id] => 20806038 [patent_doc_number] => 12670950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Bit cell based write self-time delay path [patent_app_type] => utility [patent_app_number] => 18/614460 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614460
Bit cell based write self-time delay path Mar 21, 2024 Issued
Array ( [id] => 20923809 [patent_doc_number] => 12718875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Storage circuits with tracker bitline control [patent_app_type] => utility [patent_app_number] => 18/610381 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3497 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610381
STORAGE CIRCUITS Mar 19, 2024 Pending
Array ( [id] => 20196554 [patent_doc_number] => 20250273264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MEMORY ARRAY AND MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/608939 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608939
Memory array and memory cell used as PUF memory Mar 18, 2024 Issued
Array ( [id] => 19285351 [patent_doc_number] => 20240221828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION [patent_app_type] => utility [patent_app_number] => 18/603118 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603118 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603118
High-speed multi-port memory supporting collision Mar 11, 2024 Issued
Array ( [id] => 20118214 [patent_doc_number] => 12367929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Memory device having a negative voltage circuit [patent_app_type] => utility [patent_app_number] => 18/601706 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 1121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601706
Memory device having a negative voltage circuit Mar 10, 2024 Issued
Array ( [id] => 19435731 [patent_doc_number] => 20240304229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/594104 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594104 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594104
Memory system including current copy circuit configured to copy current Mar 3, 2024 Issued
Array ( [id] => 20317962 [patent_doc_number] => 12456517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Semiconductor flash memory device with voltage control on completion of a program operation and subsequent to completion of the program operation [patent_app_type] => utility [patent_app_number] => 18/591563 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2590 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591563
Semiconductor flash memory device with voltage control on completion of a program operation and subsequent to completion of the program operation Feb 28, 2024 Issued
Array ( [id] => 20884416 [patent_doc_number] => 12700460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => SFGT storage array, storage chip and data-reading method [patent_app_type] => utility [patent_app_number] => 18/588007 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588007
SFGT STORAGE ARRAY, STORAGE CHIP AND DATA-READING METHOD Feb 26, 2024 Pending
Array ( [id] => 19452385 [patent_doc_number] => 20240312515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DUAL-RAIL MEMORY DEVICE WITH HIGH SPEED AND LOW POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 18/444776 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444776
DUAL-RAIL MEMORY DEVICE WITH HIGH SPEED AND LOW POWER CONSUMPTION Feb 18, 2024 Pending
Array ( [id] => 19452384 [patent_doc_number] => 20240312514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => NEGATIVE BIT LINE CONTROL MECHANISM [patent_app_type] => utility [patent_app_number] => 18/444754 [patent_app_country] => US [patent_app_date] => 2024-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444754
NEGATIVE BIT LINE CONTROL MECHANISM Feb 17, 2024 Pending
Array ( [id] => 20167637 [patent_doc_number] => 20250259684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => READ METHOD ENHANCEMENT TO REDUCE READ DISTURB IN MIXED-MODE MEMORY STORAGE REGIONS [patent_app_type] => utility [patent_app_number] => 18/437794 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437794
READ METHOD ENHANCEMENT TO REDUCE READ DISTURB IN MIXED-MODE MEMORY STORAGE REGIONS Feb 8, 2024 Pending
Array ( [id] => 20167624 [patent_doc_number] => 20250259671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => INCREASED THROUGHPUT FOR READS IN STATIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/436228 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436228
INCREASED THROUGHPUT FOR READS IN STATIC RANDOM ACCESS MEMORY Feb 7, 2024 Pending
Array ( [id] => 19191140 [patent_doc_number] => 20240170053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => LATCH CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/424413 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424413 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424413
Latch circuit formed by modified memory cells Jan 25, 2024 Issued
Array ( [id] => 19348888 [patent_doc_number] => 20240257852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/423980 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423980
SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL Jan 25, 2024 Pending
Array ( [id] => 19757801 [patent_doc_number] => 20250046366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => PULSE GENERATOR AND MEMORY DEVICE COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 18/420456 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420456
PULSE GENERATOR AND MEMORY DEVICE COMPRISING THE SAME Jan 22, 2024 Pending
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