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Sung Il Cho

Examiner (ID: 10363, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
626
Issued Applications
511
Pending Applications
97
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9510098 [patent_doc_number] => 20140146589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH CACHE FUNCTION IN DRAM' [patent_app_type] => utility [patent_app_number] => 13/832996 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13832996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/832996
SEMICONDUCTOR MEMORY DEVICE WITH CACHE FUNCTION IN DRAM Mar 14, 2013 Abandoned
Array ( [id] => 8719334 [patent_doc_number] => 20130070551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'Percolation Tamper Protection Circuit for Electronic Devices' [patent_app_type] => utility [patent_app_number] => 13/621741 [patent_app_country] => US [patent_app_date] => 2012-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3031 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13621741 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/621741
Percolation Tamper Protection Circuit for Electronic Devices Sep 16, 2012 Abandoned
Array ( [id] => 8616552 [patent_doc_number] => 20130021864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'Array Power Supply-Based Screening of Static Random Access Memory Cells for Bias Temperature Instability' [patent_app_type] => utility [patent_app_number] => 13/440769 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14807 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440769 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/440769
Array power supply-based screening of static random access memory cells for bias temperature instability Apr 4, 2012 Issued
Array ( [id] => 10577096 [patent_doc_number] => 09299746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Select device for cross point memory structures' [patent_app_type] => utility [patent_app_number] => 14/345295 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3149 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14345295 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/345295
Select device for cross point memory structures Oct 11, 2011 Issued
Array ( [id] => 15791043 [patent_doc_number] => 10629250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => SRAM cell having an n-well bias [patent_app_type] => utility [patent_app_number] => 13/196042 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 17713 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13196042 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/196042
SRAM cell having an n-well bias Aug 1, 2011 Issued
Array ( [id] => 8182539 [patent_doc_number] => 20120113708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'Stable SRAM Bitcell Design Utilizing Independent Gate Finfet' [patent_app_type] => utility [patent_app_number] => 12/939260 [patent_app_country] => US [patent_app_date] => 2010-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5401 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20120113708.pdf [firstpage_image] =>[orig_patent_app_number] => 12939260 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/939260
Stable SRAM bitcell design utilizing independent gate FinFET Nov 3, 2010 Issued
Array ( [id] => 12101888 [patent_doc_number] => 09858986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Integrated circuit with low power SRAM' [patent_app_type] => utility [patent_app_number] => 12/848294 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3242 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12848294 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/848294
Integrated circuit with low power SRAM Aug 1, 2010 Issued
Array ( [id] => 12968662 [patent_doc_number] => 09875788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Low-power 5T SRAM with improved stability and reduced bitcell size [patent_app_type] => utility [patent_app_number] => 12/731668 [patent_app_country] => US [patent_app_date] => 2010-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4627 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12731668 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731668
Low-power 5T SRAM with improved stability and reduced bitcell size Mar 24, 2010 Issued
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