Search

Sung Il Cho

Examiner (ID: 13560, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
629
Issued Applications
517
Pending Applications
85
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18865615 [patent_doc_number] => 20230420052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MEMORY SYSTEM HAVING SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS VERIFY OPERATIONS USING VARIOUS VERIFY VOLTAGES [patent_app_type] => utility [patent_app_number] => 18/466344 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/466344
Memory system having semiconductor memory device that performs verify operations using various verify voltages Sep 12, 2023 Issued
Array ( [id] => 19085927 [patent_doc_number] => 20240112728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/244782 [patent_app_country] => US [patent_app_date] => 2023-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18244782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/244782
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEMORY ARCHITECTURE Sep 10, 2023 Pending
Array ( [id] => 19452375 [patent_doc_number] => 20240312505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/463418 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/463418
MEMORY DEVICE Sep 7, 2023 Pending
Array ( [id] => 20441309 [patent_doc_number] => 12512149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Static random access memory (SRAM) cell with variable toggle threshold voltage and memory circuit including SRAM cells [patent_app_type] => utility [patent_app_number] => 18/459530 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3424 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459530
Static random access memory (SRAM) cell with variable toggle threshold voltage and memory circuit including SRAM cells Aug 31, 2023 Issued
Array ( [id] => 18820800 [patent_doc_number] => 20230395141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => LOW-POWER STATIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/235935 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235935
Low-power static random access memory Aug 20, 2023 Issued
Array ( [id] => 19093706 [patent_doc_number] => 11955170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Low-power static random access memory [patent_app_type] => utility [patent_app_number] => 18/235954 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 44 [patent_no_of_words] => 5223 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235954 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235954
Low-power static random access memory Aug 20, 2023 Issued
Array ( [id] => 18812230 [patent_doc_number] => 20230386567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/446072 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446072
Arrangements of memory devices and methods of operating the memory devices Aug 7, 2023 Issued
Array ( [id] => 19452362 [patent_doc_number] => 20240312492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => INTEGRATED CIRCUIT DEVICE, MEMORY CELL AND METHOD [patent_app_type] => utility [patent_app_number] => 18/366885 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366885 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366885
INTEGRATED CIRCUIT DEVICE, MEMORY CELL AND METHOD Aug 7, 2023 Pending
Array ( [id] => 20332602 [patent_doc_number] => 12462886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Method for programming a memory device to reduce retention error [patent_app_type] => utility [patent_app_number] => 18/225575 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 18524 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225575
Method for programming a memory device to reduce retention error Jul 23, 2023 Issued
Array ( [id] => 19574850 [patent_doc_number] => 20240379142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => MULTI-TIME PROGRAMMABLE MEMORY DEVICES AND METHODS [patent_app_type] => utility [patent_app_number] => 18/355359 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355359
MULTI-TIME PROGRAMMABLE MEMORY DEVICES AND METHODS Jul 18, 2023 Pending
Array ( [id] => 18757239 [patent_doc_number] => 20230360697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => NEW WAS CELL FOR SRAM HIGH-R ISSUE IN ADVANCED TECHNOLOGY NODE [patent_app_type] => utility [patent_app_number] => 18/354824 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354824
Was cell for SRAM high-R issue in advanced technology node Jul 18, 2023 Issued
Array ( [id] => 20189568 [patent_doc_number] => 12400690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Global boosting circuit [patent_app_type] => utility [patent_app_number] => 18/351629 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351629
Global boosting circuit Jul 12, 2023 Issued
Array ( [id] => 19435742 [patent_doc_number] => 20240304240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => MULTI-PORT SRAM STRUCTURES WITH CELL SIZE OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/351140 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351140
MULTI-PORT SRAM STRUCTURES WITH CELL SIZE OPTIMIZATION Jul 11, 2023 Pending
Array ( [id] => 18743097 [patent_doc_number] => 20230352085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => TIMING CONTROL CIRCUIT OF MEMORY DEVICE WITH TRACKING WORD LINE AND TRACKING BIT LINE [patent_app_type] => utility [patent_app_number] => 18/344459 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344459
Timing control circuit of memory device with tracking word line and tracking bit line Jun 28, 2023 Issued
Array ( [id] => 19687712 [patent_doc_number] => 20250006257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MEMORY DEVICE AND DATA LATCHING METHOD [patent_app_type] => utility [patent_app_number] => 18/344819 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344819
MEMORY DEVICE AND DATA LATCHING METHOD Jun 28, 2023 Pending
Array ( [id] => 19054412 [patent_doc_number] => 20240096381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT, RECEIVING DEVICE, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/336302 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336302
SEMICONDUCTOR INTEGRATED CIRCUIT, RECEIVING DEVICE, AND MEMORY SYSTEM Jun 15, 2023 Pending
Array ( [id] => 19618908 [patent_doc_number] => 20240404588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => FLY SHARED BIT LINE ON 4-CPP STATIC RANDOM ACCESS MEMORY (SRAM) CELL AND ARRAY [patent_app_type] => utility [patent_app_number] => 18/328095 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328095 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328095
FLY SHARED BIT LINE ON 4-CPP STATIC RANDOM ACCESS MEMORY (SRAM) CELL AND ARRAY Jun 1, 2023 Pending
Array ( [id] => 18661044 [patent_doc_number] => 20230307057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING IN THE SAME [patent_app_type] => utility [patent_app_number] => 18/205149 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205149
Nonvolatile memory device and method of programming in the same Jun 1, 2023 Issued
Array ( [id] => 19639495 [patent_doc_number] => 12170108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Circuitry for power management assertion [patent_app_type] => utility [patent_app_number] => 18/325170 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325170
Circuitry for power management assertion May 29, 2023 Issued
Array ( [id] => 19356704 [patent_doc_number] => 12057159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Memory system with burst mode having logic gates as sense elements [patent_app_type] => utility [patent_app_number] => 18/323250 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323250
Memory system with burst mode having logic gates as sense elements May 23, 2023 Issued
Menu