Search

Sung Il Cho

Examiner (ID: 13560, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
629
Issued Applications
517
Pending Applications
85
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20305196 [patent_doc_number] => 12451192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Non-volatile memory device with high voltage region and low voltage region [patent_app_type] => utility [patent_app_number] => 18/201331 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201331 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201331
Non-volatile memory device with high voltage region and low voltage region May 23, 2023 Issued
Array ( [id] => 18820839 [patent_doc_number] => 20230395180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => ROW DECODER CIRCUIT, MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/133319 [patent_app_country] => US [patent_app_date] => 2023-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/133319
Row decoder circuit, memory device and memory system Apr 10, 2023 Issued
Array ( [id] => 18540907 [patent_doc_number] => 20230246018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => MEMORY CELL ARRAY AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/295134 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295134
Memory cell array and method of operating same Apr 2, 2023 Issued
Array ( [id] => 20305204 [patent_doc_number] => 12451200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Memory device related to verifying memory cells in an erase state and method of operating the memory device [patent_app_type] => utility [patent_app_number] => 18/191807 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191807
Memory device related to verifying memory cells in an erase state and method of operating the memory device Mar 27, 2023 Issued
Array ( [id] => 19951091 [patent_doc_number] => 12322461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Dielectric film based one-time programmable (OTP) memory cell [patent_app_type] => utility [patent_app_number] => 18/186734 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 5629 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186734
Dielectric film based one-time programmable (OTP) memory cell Mar 19, 2023 Issued
Array ( [id] => 20276429 [patent_doc_number] => 12446218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Memory cell with contiguous P-well and N-well structures [patent_app_type] => utility [patent_app_number] => 18/185575 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 3086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/185575
Memory cell with contiguous P-well and N-well structures Mar 16, 2023 Issued
Array ( [id] => 19828571 [patent_doc_number] => 12249362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Single plate configuration and memory array operation [patent_app_type] => utility [patent_app_number] => 18/120133 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16950 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120133 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120133
Single plate configuration and memory array operation Mar 9, 2023 Issued
Array ( [id] => 19687683 [patent_doc_number] => 20250006228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => Storage Array, and Interconnection Structure and Method for Operating Thereof [patent_app_type] => utility [patent_app_number] => 18/729153 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18729153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/729153
Storage array, and interconnection structure and method for operating thereof Mar 9, 2023 Issued
Array ( [id] => 20203927 [patent_doc_number] => 12406710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Forming method of memory device [patent_app_type] => utility [patent_app_number] => 18/180003 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1013 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180003
Forming method of memory device Mar 6, 2023 Issued
Array ( [id] => 19160845 [patent_doc_number] => 20240153552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => MEMORY ARRAY FOR COMPUTE-IN-MEMORY AND THE OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/175895 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175895
MEMORY ARRAY FOR COMPUTE-IN-MEMORY AND THE OPERATING METHOD THEREOF Feb 27, 2023 Pending
Array ( [id] => 18961148 [patent_doc_number] => 20240049475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => MAGNETIC MEMORY [patent_app_type] => utility [patent_app_number] => 18/176464 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176464
Magnetic memory including transistors and magnetoresistive elements respectively connected between a conductive plate and a conductive line and additional transistors each connected between the conductive line and another conductive line Feb 27, 2023 Issued
Array ( [id] => 18500290 [patent_doc_number] => 20230223075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => PSEUDO-TRIPLE-PORT SRAM DATAPATHS [patent_app_type] => utility [patent_app_number] => 18/175023 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175023 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175023
Method of pseudo-triple-port SRAM datapaths Feb 26, 2023 Issued
Array ( [id] => 18848524 [patent_doc_number] => 20230410928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Design for Testability Circuit and Read and Write Path Decoupling Circuit of SRAM [patent_app_type] => utility [patent_app_number] => 18/172436 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172436 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172436
Testability circuit and read and write path decoupling circuit of SRAM Feb 21, 2023 Issued
Array ( [id] => 19070815 [patent_doc_number] => 20240105241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => MEMORY DEVICE INCLUDING SEPARATE NEGATIVE BIT LINE [patent_app_type] => utility [patent_app_number] => 18/170426 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170426
Memory device including separate negative bit line Feb 15, 2023 Issued
Array ( [id] => 20118213 [patent_doc_number] => 12367928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/169463 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 9764 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169463
Semiconductor device Feb 14, 2023 Issued
Array ( [id] => 18661045 [patent_doc_number] => 20230307058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => PRE-READ OPERATION FOR MULTI-PASS PROGRAMMING OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/110303 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110303 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110303
PRE-READ OPERATION FOR MULTI-PASS PROGRAMMING OF MEMORY DEVICES Feb 14, 2023 Pending
Array ( [id] => 19972246 [patent_doc_number] => 12340864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Interface level-shifter dual-rail memory architecture [patent_app_type] => utility [patent_app_number] => 18/107450 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 1140 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107450 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107450
Interface level-shifter dual-rail memory architecture Feb 7, 2023 Issued
Array ( [id] => 18439696 [patent_doc_number] => 20230186991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR FLASH MEMORY DEVICE WITH VOLTAGE CONTROL ON COMPLETION OF A PROGRAM OPERATION AND SUBSEQUENT TO COMPLETION OF THE PROGRAM OPERATION [patent_app_type] => utility [patent_app_number] => 18/106520 [patent_app_country] => US [patent_app_date] => 2023-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/106520
Semiconductor flash memory device with voltage control on completion of a program operation and subsequent to completion of the program operation Feb 6, 2023 Issued
Array ( [id] => 18423656 [patent_doc_number] => 20230178120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => MEMORY DEVICE WITH CHARGE-RECYCLING ARRANGEMENT AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/165415 [patent_app_country] => US [patent_app_date] => 2023-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/165415
MEMORY DEVICE WITH CHARGE-RECYCLING ARRANGEMENT AND METHOD OF OPERATING THE SAME Feb 6, 2023 Pending
Array ( [id] => 19812187 [patent_doc_number] => 12243595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Solid-state drive controller and circuit controller [patent_app_type] => utility [patent_app_number] => 18/104679 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2102 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104679
Solid-state drive controller and circuit controller Jan 31, 2023 Issued
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