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Sung Il Cho

Examiner (ID: 13560, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
629
Issued Applications
517
Pending Applications
85
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18813563 [patent_doc_number] => 20230387900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => DELAY CONTROL CIRCUIT AND A MEMORY MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/101653 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101653
Delay control circuit and a memory module including the same Jan 25, 2023 Issued
Array ( [id] => 19022866 [patent_doc_number] => 20240079037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => MEMORY DEVICE FOR SUPPORTING STABLE DATA TRANSFER AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/159685 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18159685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/159685
Memory device for supporting stable data transfer and memory system including the same Jan 25, 2023 Issued
Array ( [id] => 18394565 [patent_doc_number] => 20230162786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MEMORY DEVICE HAVING A NEGATIVE VOLTAGE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/158076 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158076 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158076
Memory device having a negative voltage circuit Jan 22, 2023 Issued
Array ( [id] => 18423655 [patent_doc_number] => 20230178119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => DATA STORAGE CIRCUIT AND CONTROL METHOD THEREOF, AND STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 18/155084 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155084 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155084
DATA STORAGE CIRCUIT AND CONTROL METHOD THEREOF, AND STORAGE APPARATUS Jan 16, 2023 Pending
Array ( [id] => 18898335 [patent_doc_number] => 20240013820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => STRUCTURE FOR DATA TRANSMISSION, METHOD FOR DATA TRANSMISSION, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/154935 [patent_app_country] => US [patent_app_date] => 2023-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154935
Structure for data transmission, method for data transmission, and memory Jan 15, 2023 Issued
Array ( [id] => 19917714 [patent_doc_number] => 12293084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Operating method for a memory, a memory, and a memory system to improve programming efficiency [patent_app_type] => utility [patent_app_number] => 18/148763 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6737 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148763 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148763
Operating method for a memory, a memory, and a memory system to improve programming efficiency Dec 29, 2022 Issued
Array ( [id] => 18324007 [patent_doc_number] => 20230122135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => STATIC RANDOM ACCESS MEMORY WITH ADAPTIVE PRECHARGE SIGNAL GENERATED IN RESPONSE TO TRACKING OPERATION [patent_app_type] => utility [patent_app_number] => 18/068881 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068881
Static random access memory with adaptive precharge signal generated in response to tracking operation Dec 19, 2022 Issued
Array ( [id] => 19858054 [patent_doc_number] => 12260904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Memory device with additional write bit lines [patent_app_type] => utility [patent_app_number] => 18/066306 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066306 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066306
Memory device with additional write bit lines Dec 14, 2022 Issued
Array ( [id] => 18941603 [patent_doc_number] => 20240036742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => PAGE BUFFER, SEMICONDUCTOR MEMORY HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/077915 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077915 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077915
Page buffer, semiconductor memory having the same, and operating method thereof Dec 7, 2022 Issued
Array ( [id] => 19191115 [patent_doc_number] => 20240170028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/992938 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992938
Memory device having row driver circuits for reducing leakage currents during power off Nov 22, 2022 Issued
Array ( [id] => 19175834 [patent_doc_number] => 20240161808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/988186 [patent_app_country] => US [patent_app_date] => 2022-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/988186
DDR PHY CRITICAL CLOCK SWITCHING AND GATING ARCHITECTURE Nov 15, 2022 Pending
Array ( [id] => 18423672 [patent_doc_number] => 20230178136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => MEMORY DEVICE DETECTING WEAKNESS OF OPERATION PATTERN AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/052469 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052469
Memory device detecting weakness of operation pattern and method of operating the same Nov 2, 2022 Issued
Array ( [id] => 18252038 [patent_doc_number] => 20230079077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => WORD LINE VOLTAGE DETECTION CIRCUIT FOR ENCHANCED READ OPERATION [patent_app_type] => utility [patent_app_number] => 18/047097 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047097 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047097
WORD LINE VOLTAGE DETECTION CIRCUIT FOR ENCHANCED READ OPERATION Oct 16, 2022 Pending
Array ( [id] => 19046465 [patent_doc_number] => 11935584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Sense amplifier drivers, and related devices, systems, and methods [patent_app_type] => utility [patent_app_number] => 17/935825 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 11298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17935825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/935825
Sense amplifier drivers, and related devices, systems, and methods Sep 26, 2022 Issued
Array ( [id] => 19073474 [patent_doc_number] => 20240107900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => PHASE CHANGE MEMORY CELL SIDEWALL HEATER [patent_app_type] => utility [patent_app_number] => 17/934212 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934212
PHASE CHANGE MEMORY CELL SIDEWALL HEATER Sep 21, 2022 Pending
Array ( [id] => 19022892 [patent_doc_number] => 20240079063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => DYNAMIC WORD LINE BOOSTING DURING PROGRAMMING OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/939160 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939160
Dynamic word line boosting during programming of a memory device Sep 6, 2022 Issued
Array ( [id] => 18935222 [patent_doc_number] => 11887660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Time-interleaving sensing scheme for pseudo dual-port memory [patent_app_type] => utility [patent_app_number] => 17/894191 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3077 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894191
Time-interleaving sensing scheme for pseudo dual-port memory Aug 23, 2022 Issued
Array ( [id] => 20495172 [patent_doc_number] => 12537048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor device having memory cell array divided into plural memory mats [patent_app_type] => utility [patent_app_number] => 17/821448 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 1115 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821448
Semiconductor device having memory cell array divided into plural memory mats Aug 21, 2022 Issued
Array ( [id] => 19812171 [patent_doc_number] => 12243579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Layouts for sense amplifiers and related apparatuses and systems [patent_app_type] => utility [patent_app_number] => 17/819724 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819724
Layouts for sense amplifiers and related apparatuses and systems Aug 14, 2022 Issued
Array ( [id] => 18364786 [patent_doc_number] => 20230146377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/885822 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885822
Memory device and memory system including the same Aug 10, 2022 Issued
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