Search

Sung Il Cho

Examiner (ID: 13560, Phone: (571)270-0137 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
629
Issued Applications
517
Pending Applications
85
Abandoned Applications
50

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19934883 [patent_doc_number] => 12308091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Pseudo-2-port memory with dual pre-charge circuits [patent_app_type] => utility [patent_app_number] => 17/643038 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643038
Pseudo-2-port memory with dual pre-charge circuits Dec 6, 2021 Issued
Array ( [id] => 18238243 [patent_doc_number] => 20230070554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MULTI TIME PROGRAM DEVICE WITH POWER SWITCH AND NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/544260 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544260
Multi time program device with power switch and non-volatile memory Dec 6, 2021 Issued
Array ( [id] => 18423677 [patent_doc_number] => 20230178141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => CIRCUITRY INCLUDING A LEVEL SHIFTER AND LOGIC, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/457570 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457570
Circuitry including a level shifter and logic, configured to receive a power up reset signal, and associated methods, devices, and systems Dec 2, 2021 Issued
Array ( [id] => 18241237 [patent_doc_number] => 20230073548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/537395 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537395
MTJ operation methods employing opposite polarity recovery pulse Nov 28, 2021 Issued
Array ( [id] => 17630777 [patent_doc_number] => 20220165792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => METHOD FOR MANUFACTURING A MICROELECTRONIC DEVICE COMPRISING A PLURALITY OF RESISTIVE MEMORY POINTS CONFIGURED TO FORM A PHYSICAL UNCLONABLE FUNCTION AND SAID DEVICE [patent_app_type] => utility [patent_app_number] => 17/533545 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/533545
Method for manufacturing a microelectronic device comprising a plurality of resistive memory points configured to form a physical unclonable function and said device Nov 22, 2021 Issued
Array ( [id] => 19900040 [patent_doc_number] => 12277972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Source line configuration for a memory device [patent_app_type] => utility [patent_app_number] => 17/512597 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11966 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512597
Source line configuration for a memory device Oct 26, 2021 Issued
Array ( [id] => 18669711 [patent_doc_number] => 11776621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory device for increasing write margin during write operation and reducing current leakage during standby operation and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/508768 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5135 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508768 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508768
Memory device for increasing write margin during write operation and reducing current leakage during standby operation and operation method thereof Oct 21, 2021 Issued
Array ( [id] => 18967218 [patent_doc_number] => 11900996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Memory structure with self-adjusting capacitive coupling-based read and write assist [patent_app_type] => utility [patent_app_number] => 17/504558 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504558
Memory structure with self-adjusting capacitive coupling-based read and write assist Oct 18, 2021 Issued
Array ( [id] => 18112633 [patent_doc_number] => 20230005513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => INTERFACE TRANSFORMER AND MULTIPORT STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/501997 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501997 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501997
INTERFACE TRANSFORMER AND MULTIPORT STORAGE DEVICE Oct 13, 2021 Abandoned
Array ( [id] => 17551315 [patent_doc_number] => 20220122657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => DEVICE AND METHOD FOR READING DATA FROM MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/494683 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494683
Device and method for reading data from memory cells Oct 4, 2021 Issued
Array ( [id] => 17507301 [patent_doc_number] => 20220100404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CIRCUIT PARTITIONING FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/493988 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493988 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493988
Circuit partitioning for a memory device Oct 4, 2021 Issued
Array ( [id] => 18285135 [patent_doc_number] => 20230100607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SRAM POWER SAVINGS AND WRITE ASSIST [patent_app_type] => utility [patent_app_number] => 17/488519 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488519 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488519
SRAM power savings and write assist Sep 28, 2021 Issued
Array ( [id] => 17566305 [patent_doc_number] => 20220130454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => CIRCUITRY FOR ADJUSTING RETENTION VOLTAGE OF A STATIC RANDOM ACCESS MEMORY (SRAM) [patent_app_type] => utility [patent_app_number] => 17/483501 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483501
Circuitry for adjusting retention voltage of a static random access memory (SRAM) Sep 22, 2021 Issued
Array ( [id] => 18080731 [patent_doc_number] => 20220406343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => CONTROL CIRCUIT FOR ADJUSTING TIMING OF SENSE AMPLIFIER ENABLE SIGNAL, AND SENSE ENABLE CIRCUIT AND METHOD FOR ENABLING SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/483450 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483450
CONTROL CIRCUIT FOR ADJUSTING TIMING OF SENSE AMPLIFIER ENABLE SIGNAL, AND SENSE ENABLE CIRCUIT AND METHOD FOR ENABLING SENSE AMPLIFIER Sep 22, 2021 Abandoned
Array ( [id] => 18266035 [patent_doc_number] => 20230087277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MEMORY WITH A SENSE AMPLIFIER ISOLATION SCHEME FOR ENHANCING MEMORY READ BANDWIDTH [patent_app_type] => utility [patent_app_number] => 17/481601 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481601 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481601
Memory with a sense amplifier isolation scheme for enhancing memory read bandwidth Sep 21, 2021 Issued
Array ( [id] => 19183583 [patent_doc_number] => 11990179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Memory device using a plurality of supply voltages and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/478629 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9399 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478629
Memory device using a plurality of supply voltages and operating method thereof Sep 16, 2021 Issued
Array ( [id] => 19475497 [patent_doc_number] => 12105585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Method of equalizing bit error rates of memory device [patent_app_type] => utility [patent_app_number] => 17/478597 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 38 [patent_no_of_words] => 17955 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478597
Method of equalizing bit error rates of memory device Sep 16, 2021 Issued
Array ( [id] => 18253552 [patent_doc_number] => 20230080591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => LOW STANDBY LEAKAGE IMPLEMENTATION FOR STATIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/475386 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/475386
Low standby leakage implementation for static random access memory Sep 14, 2021 Issued
Array ( [id] => 17795295 [patent_doc_number] => 20220254387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SENSE AMPLIFIER INCLUDING PRE-AMPLIFIER CIRCUIT AND MEMORY DEVICE INCLUDING SAME [patent_app_type] => utility [patent_app_number] => 17/469948 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469948
Sense amplifier including pre-amplifier circuit and memory device including same Sep 8, 2021 Issued
Array ( [id] => 17948990 [patent_doc_number] => 20220336009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Circuitry for Power Management Assertion [patent_app_type] => utility [patent_app_number] => 17/468771 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468771
Circuitry for power management assertion Sep 7, 2021 Issued
Menu