Search

Suresh Memula

Examiner (ID: 1891, Phone: (571)272-8046 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1443
Issued Applications
1267
Pending Applications
54
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9029806 [patent_doc_number] => 08539404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Functional simulation redundancy reduction by state comparison and pruning' [patent_app_type] => utility [patent_app_number] => 13/241496 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241496 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241496
Functional simulation redundancy reduction by state comparison and pruning Sep 22, 2011 Issued
Array ( [id] => 8805027 [patent_doc_number] => 08443311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Flare value calculation method, flare correction method, and computer program product' [patent_app_type] => utility [patent_app_number] => 13/238616 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5787 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238616 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238616
Flare value calculation method, flare correction method, and computer program product Sep 20, 2011 Issued
Array ( [id] => 8959180 [patent_doc_number] => 08504974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-06 [patent_title] => 'Analysis of circuit designs' [patent_app_type] => utility [patent_app_number] => 13/232176 [patent_app_country] => US [patent_app_date] => 2011-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4754 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13232176 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/232176
Analysis of circuit designs Sep 13, 2011 Issued
Array ( [id] => 11880264 [patent_doc_number] => 09751421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Charging system for vehicle, method for charging vehicle, power supply system, and power supply method' [patent_app_type] => utility [patent_app_number] => 14/342616 [patent_app_country] => US [patent_app_date] => 2011-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6163 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14342616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/342616
Charging system for vehicle, method for charging vehicle, power supply system, and power supply method Sep 7, 2011 Issued
Array ( [id] => 8678831 [patent_doc_number] => 08386969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method for designing overlay targets and method and system for measuring overlay error using the same' [patent_app_type] => utility [patent_app_number] => 13/225690 [patent_app_country] => US [patent_app_date] => 2011-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 2930 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13225690 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/225690
Method for designing overlay targets and method and system for measuring overlay error using the same Sep 5, 2011 Issued
Array ( [id] => 8667681 [patent_doc_number] => 08381154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method of making apparatus for computing multiple sum of products' [patent_app_type] => utility [patent_app_number] => 13/199606 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5570 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13199606 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/199606
Method of making apparatus for computing multiple sum of products Sep 1, 2011 Issued
Array ( [id] => 8878888 [patent_doc_number] => 08473873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Multi-patterning method' [patent_app_type] => utility [patent_app_number] => 13/224486 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224486
Multi-patterning method Sep 1, 2011 Issued
Array ( [id] => 8408021 [patent_doc_number] => 20120240090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'CLOCK TREE DESIGNING APPARATUS AND CLOCK TREE DESIGNING METHOD' [patent_app_type] => utility [patent_app_number] => 13/224186 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224186 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224186
CLOCK TREE DESIGNING APPARATUS AND CLOCK TREE DESIGNING METHOD Aug 31, 2011 Abandoned
Array ( [id] => 8787177 [patent_doc_number] => 08434033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Mask assignment for multiple patterning lithography' [patent_app_type] => utility [patent_app_number] => 13/223706 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13223706 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/223706
Mask assignment for multiple patterning lithography Aug 31, 2011 Issued
Array ( [id] => 7793141 [patent_doc_number] => 20120054697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'LIGHT SOURCE SHAPE CALCULATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/222016 [patent_app_country] => US [patent_app_date] => 2011-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054697.pdf [firstpage_image] =>[orig_patent_app_number] => 13222016 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/222016
LIGHT SOURCE SHAPE CALCULATION METHOD Aug 30, 2011 Abandoned
Array ( [id] => 8383410 [patent_doc_number] => 20120227023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'REAL TIME DRC ASSISTANCE FOR MANUAL LAYOUT EDITING' [patent_app_type] => utility [patent_app_number] => 13/219524 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 25737 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219524 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219524
Real time DRC assistance for manual layout editing Aug 25, 2011 Issued
Array ( [id] => 8728511 [patent_doc_number] => 08407653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-26 [patent_title] => 'Method and system of estimating a derating factor for soft errors in a circuit' [patent_app_type] => utility [patent_app_number] => 13/217496 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5610 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217496 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217496
Method and system of estimating a derating factor for soft errors in a circuit Aug 24, 2011 Issued
Array ( [id] => 7658577 [patent_doc_number] => 20110307846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD' [patent_app_type] => utility [patent_app_number] => 13/216362 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307846.pdf [firstpage_image] =>[orig_patent_app_number] => 13216362 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/216362
Methods and system for analysis and management of parametric yield Aug 23, 2011 Issued
Array ( [id] => 8810430 [patent_doc_number] => 08448097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'High performance DRC checking algorithm for derived layer based rules' [patent_app_type] => utility [patent_app_number] => 13/211211 [patent_app_country] => US [patent_app_date] => 2011-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 21935 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13211211 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/211211
High performance DRC checking algorithm for derived layer based rules Aug 15, 2011 Issued
Array ( [id] => 8568855 [patent_doc_number] => 20120331426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'CELL ARCHITECTURE AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/207506 [patent_app_country] => US [patent_app_date] => 2011-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4758 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13207506 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/207506
Cell architecture and method Aug 10, 2011 Issued
Array ( [id] => 8839320 [patent_doc_number] => 20130134948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'VANADIUM BORIDE AIR MULTIPLE ELECTRON HIGH CAPACITY BATTERY' [patent_app_type] => utility [patent_app_number] => 13/814904 [patent_app_country] => US [patent_app_date] => 2011-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13814904 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/814904
Vanadium boride air multiple electron high capacity battery Aug 9, 2011 Issued
Array ( [id] => 8661388 [patent_doc_number] => 20130042217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 13/205186 [patent_app_country] => US [patent_app_date] => 2011-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6827 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13205186 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/205186
Structural migration of integrated circuit layout Aug 7, 2011 Issued
Array ( [id] => 8650664 [patent_doc_number] => 20130036394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'Vectorless IVD Analysis Prior to Tapeout to Prevent Scan Test Failure Due to Voltage Drop' [patent_app_type] => utility [patent_app_number] => 13/197146 [patent_app_country] => US [patent_app_date] => 2011-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5439 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13197146 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/197146
Vectorless IVD analysis prior to tapeout to prevent scan test failure due to voltage drop Aug 2, 2011 Issued
Array ( [id] => 8728501 [patent_doc_number] => 08407643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-26 [patent_title] => 'Techniques and apparatus to validate an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 13/194916 [patent_app_country] => US [patent_app_date] => 2011-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4686 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13194916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/194916
Techniques and apparatus to validate an integrated circuit design Jul 29, 2011 Issued
Array ( [id] => 8752259 [patent_doc_number] => 08418103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Nonlinear approach to scaling circuit behaviors for electronic design automation' [patent_app_type] => utility [patent_app_number] => 13/193396 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3430 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193396 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193396
Nonlinear approach to scaling circuit behaviors for electronic design automation Jul 27, 2011 Issued
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