Search

Suresh Memula

Examiner (ID: 1891, Phone: (571)272-8046 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1443
Issued Applications
1267
Pending Applications
54
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8639715 [patent_doc_number] => 20130031518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'Hybrid Hotspot Detection' [patent_app_type] => utility [patent_app_number] => 13/191436 [patent_app_country] => US [patent_app_date] => 2011-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6652 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/191436
Hybrid hotspot detection Jul 25, 2011 Issued
Array ( [id] => 8011137 [patent_doc_number] => 08086987 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-27 [patent_title] => 'Method for resolving overloads in autorouting physical interconnections' [patent_app_type] => utility [patent_app_number] => 13/188176 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8244 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086987.pdf [firstpage_image] =>[orig_patent_app_number] => 13188176 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188176
Method for resolving overloads in autorouting physical interconnections Jul 20, 2011 Issued
Array ( [id] => 8574898 [patent_doc_number] => 08341562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Reducing metal pits through optical proximity correction' [patent_app_type] => utility [patent_app_number] => 13/188166 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3328 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13188166 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188166
Reducing metal pits through optical proximity correction Jul 20, 2011 Issued
Array ( [id] => 8001371 [patent_doc_number] => 08082533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Method for resolving overloads in autorouting physical interconnections' [patent_app_type] => utility [patent_app_number] => 13/188149 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8244 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082533.pdf [firstpage_image] =>[orig_patent_app_number] => 13188149 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188149
Method for resolving overloads in autorouting physical interconnections Jul 20, 2011 Issued
Array ( [id] => 8378420 [patent_doc_number] => 08261226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-09-04 [patent_title] => 'Network flow based module bottom surface metal pin assignment' [patent_app_type] => utility [patent_app_number] => 13/187196 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 11478 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187196 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187196
Network flow based module bottom surface metal pin assignment Jul 19, 2011 Issued
Array ( [id] => 7813541 [patent_doc_number] => 08136079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Effective gate length circuit modeling based on concurrent length and mobility analysis' [patent_app_type] => utility [patent_app_number] => 13/187201 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6677 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136079.pdf [firstpage_image] =>[orig_patent_app_number] => 13187201 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187201
Effective gate length circuit modeling based on concurrent length and mobility analysis Jul 19, 2011 Issued
Array ( [id] => 7563103 [patent_doc_number] => 20110276937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Integrated Circuit Routing with Compaction' [patent_app_type] => utility [patent_app_number] => 13/186258 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7804 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276937.pdf [firstpage_image] =>[orig_patent_app_number] => 13186258 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/186258
Integrated circuit routing with compaction Jul 18, 2011 Issued
Array ( [id] => 10591091 [patent_doc_number] => 09312714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Control device and control method, power generation device and power generation method, power storage device and power storage method, and power control system' [patent_app_type] => utility [patent_app_number] => 13/810539 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17726 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13810539 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/810539
Control device and control method, power generation device and power generation method, power storage device and power storage method, and power control system Jul 14, 2011 Issued
Array ( [id] => 8925913 [patent_doc_number] => 20130181673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'CHARGER FOR A BATTERY FOR SUPPLYING POWER TO A DRIVE MOTOR OF A MOTOR VEHICLE' [patent_app_type] => utility [patent_app_number] => 13/809731 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1744 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13809731 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/809731
CHARGER FOR A BATTERY FOR SUPPLYING POWER TO A DRIVE MOTOR OF A MOTOR VEHICLE Jul 11, 2011 Abandoned
Array ( [id] => 8552411 [patent_doc_number] => 08327310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Method and software tool for analyzing and reducing the failure rate of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/177916 [patent_app_country] => US [patent_app_date] => 2011-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6496 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13177916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/177916
Method and software tool for analyzing and reducing the failure rate of an integrated circuit Jul 6, 2011 Issued
Array ( [id] => 7770634 [patent_doc_number] => 20120036490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'INFORMATION PROCESSING DEVICE AND DESIGN SUPPORTING METHOD' [patent_app_type] => utility [patent_app_number] => 13/177096 [patent_app_country] => US [patent_app_date] => 2011-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 16826 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20120036490.pdf [firstpage_image] =>[orig_patent_app_number] => 13177096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/177096
Information processing device and design supporting method Jul 5, 2011 Issued
Array ( [id] => 7504015 [patent_doc_number] => 20110265050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'REPRESENTING BINARY CODE AS A CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/175924 [patent_app_country] => US [patent_app_date] => 2011-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265050.pdf [firstpage_image] =>[orig_patent_app_number] => 13175924 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175924
REPRESENTING BINARY CODE AS A CIRCUIT Jul 3, 2011 Abandoned
Array ( [id] => 8438324 [patent_doc_number] => 08286109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-09 [patent_title] => 'Method and apparatus for performing incremental delay annotation' [patent_app_type] => utility [patent_app_number] => 13/118471 [patent_app_country] => US [patent_app_date] => 2011-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118471 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/118471
Method and apparatus for performing incremental delay annotation May 29, 2011 Issued
Array ( [id] => 9639872 [patent_doc_number] => 20140217982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'ELECTRIC STORAGE CELL CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/119388 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9018 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14119388 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/119388
Electric storage cell control circuit May 22, 2011 Issued
Array ( [id] => 8285844 [patent_doc_number] => 08219961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Method for compensation of process-induced performance variation in a MOSFET integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/112837 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2679 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13112837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112837
Method for compensation of process-induced performance variation in a MOSFET integrated circuit May 19, 2011 Issued
Array ( [id] => 8716259 [patent_doc_number] => 08402412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effect' [patent_app_type] => utility [patent_app_number] => 13/112896 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9323 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13112896 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112896
Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effect May 19, 2011 Issued
Array ( [id] => 8485276 [patent_doc_number] => 20120284683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'TIMING DRIVEN ROUTING IN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 13/102776 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102776 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/102776
Timing driven routing in integrated circuit design May 5, 2011 Issued
Array ( [id] => 5960943 [patent_doc_number] => 20110185330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS' [patent_app_type] => utility [patent_app_number] => 13/080716 [patent_app_country] => US [patent_app_date] => 2011-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9690 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185330.pdf [firstpage_image] =>[orig_patent_app_number] => 13080716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080716
Metal wiring structure for integration with through substrate vias Apr 5, 2011 Issued
Array ( [id] => 8787183 [patent_doc_number] => 08434039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Method for incorporating pattern dependent effects in circuit simulations' [patent_app_type] => utility [patent_app_number] => 13/073291 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4371 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13073291 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/073291
Method for incorporating pattern dependent effects in circuit simulations Mar 27, 2011 Issued
Array ( [id] => 7493382 [patent_doc_number] => 20110239174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'METHOD AND APPARATUS FOR LAYING OUT POWER WIRING OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/071076 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5380 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239174.pdf [firstpage_image] =>[orig_patent_app_number] => 13071076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/071076
Method and apparatus for laying out power wiring of semiconductor device Mar 23, 2011 Issued
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