
Suresh Suryawanshi
Examiner (ID: 4736, Phone: (571)272-3668 , Office: P/2118 )
| Most Active Art Unit | 2116 |
| Art Unit(s) | 2118, 2121, 2116, 2115, 2185 |
| Total Applications | 1546 |
| Issued Applications | 1324 |
| Pending Applications | 89 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7510475
[patent_doc_number] => 08037323
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-11
[patent_title] => 'System and method for using an ethernet physical layer device to identify cabling topologies'
[patent_app_type] => utility
[patent_app_number] => 12/049254
[patent_app_country] => US
[patent_app_date] => 2008-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3271
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/037/08037323.pdf
[firstpage_image] =>[orig_patent_app_number] => 12049254
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/049254 | System and method for using an ethernet physical layer device to identify cabling topologies | Mar 13, 2008 | Issued |
Array
(
[id] => 4684034
[patent_doc_number] => 20080250260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-09
[patent_title] => 'INFORMATION PROCESSING APPARATUS, SCHEDULER, AND SCHEDULE CONTROL METHOD OF INFORMATION PROCESSING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/047802
[patent_app_country] => US
[patent_app_date] => 2008-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4478
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20080250260.pdf
[firstpage_image] =>[orig_patent_app_number] => 12047802
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/047802 | INFORMATION PROCESSING APPARATUS, SCHEDULER, AND SCHEDULE CONTROL METHOD OF INFORMATION PROCESSING APPARATUS | Mar 12, 2008 | Abandoned |
Array
(
[id] => 5535274
[patent_doc_number] => 20090235062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'METHOD AND APPARATUS FOR CONTROLLING OPERATING PARAMETERS IN A COMPUTER SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/048115
[patent_app_country] => US
[patent_app_date] => 2008-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4473
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20090235062.pdf
[firstpage_image] =>[orig_patent_app_number] => 12048115
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/048115 | Method and apparatus for controlling operating parameters in a computer system | Mar 12, 2008 | Issued |
Array
(
[id] => 5381403
[patent_doc_number] => 20090193242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-30
[patent_title] => 'COMPUTER SYSTEM WITH DUAL BASIC INPUT OUTPUT SYSTEM AND OPERATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/047136
[patent_app_country] => US
[patent_app_date] => 2008-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3405
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20090193242.pdf
[firstpage_image] =>[orig_patent_app_number] => 12047136
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/047136 | Computer system with dual basic input output system and operation method thereof | Mar 11, 2008 | Issued |
Array
(
[id] => 350825
[patent_doc_number] => 07496772
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-02-24
[patent_title] => 'Method for estimating total power requirement in a computer system'
[patent_app_type] => utility
[patent_app_number] => 12/041669
[patent_app_country] => US
[patent_app_date] => 2008-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2452
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/496/07496772.pdf
[firstpage_image] =>[orig_patent_app_number] => 12041669
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/041669 | Method for estimating total power requirement in a computer system | Mar 3, 2008 | Issued |
Array
(
[id] => 180052
[patent_doc_number] => 07657768
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Disk array optimizing the drive operation time'
[patent_app_type] => utility
[patent_app_number] => 12/038566
[patent_app_country] => US
[patent_app_date] => 2008-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6205
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/657/07657768.pdf
[firstpage_image] =>[orig_patent_app_number] => 12038566
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/038566 | Disk array optimizing the drive operation time | Feb 26, 2008 | Issued |
Array
(
[id] => 5512540
[patent_doc_number] => 20090212844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'Information Handling System Port Security'
[patent_app_type] => utility
[patent_app_number] => 12/037458
[patent_app_country] => US
[patent_app_date] => 2008-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4011
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20090212844.pdf
[firstpage_image] =>[orig_patent_app_number] => 12037458
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/037458 | Information handling system port security | Feb 25, 2008 | Issued |
Array
(
[id] => 4836694
[patent_doc_number] => 20080133946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'METHODS AND APPARATUS FOR PROVISIONING PHANTOM POWER TO REMOTE DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/015590
[patent_app_country] => US
[patent_app_date] => 2008-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5043
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20080133946.pdf
[firstpage_image] =>[orig_patent_app_number] => 12015590
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/015590 | Methods and apparatus for provisioning phantom power to remote devices | Jan 16, 2008 | Issued |
Array
(
[id] => 5280668
[patent_doc_number] => 20090132800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-21
[patent_title] => 'METHOD FOR ADJUSTING SETUP DEFAULT VALUE OF BIOS AND MAIN BOARD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/972386
[patent_app_country] => US
[patent_app_date] => 2008-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5372
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20090132800.pdf
[firstpage_image] =>[orig_patent_app_number] => 11972386
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/972386 | Method for adjusting setup default value of BIOS and main board thereof | Jan 9, 2008 | Issued |
Array
(
[id] => 4606367
[patent_doc_number] => 07987353
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Remote BIOS for servers and blades'
[patent_app_type] => utility
[patent_app_number] => 11/971700
[patent_app_country] => US
[patent_app_date] => 2008-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3733
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/987/07987353.pdf
[firstpage_image] =>[orig_patent_app_number] => 11971700
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/971700 | Remote BIOS for servers and blades | Jan 8, 2008 | Issued |
Array
(
[id] => 4586789
[patent_doc_number] => 07849346
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-12-07
[patent_title] => 'Dynamic programmable delay selection circuit and method'
[patent_app_type] => utility
[patent_app_number] => 11/963076
[patent_app_country] => US
[patent_app_date] => 2007-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4711
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/849/07849346.pdf
[firstpage_image] =>[orig_patent_app_number] => 11963076
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/963076 | Dynamic programmable delay selection circuit and method | Dec 20, 2007 | Issued |
Array
(
[id] => 86700
[patent_doc_number] => 07747885
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-29
[patent_title] => 'Electronic device with serial ATA interface and power saving method for serial ATA buses'
[patent_app_type] => utility
[patent_app_number] => 11/956996
[patent_app_country] => US
[patent_app_date] => 2007-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8652
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/747/07747885.pdf
[firstpage_image] =>[orig_patent_app_number] => 11956996
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/956996 | Electronic device with serial ATA interface and power saving method for serial ATA buses | Dec 13, 2007 | Issued |
Array
(
[id] => 27332
[patent_doc_number] => 07802086
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Method for recovering BIOS chip in a computer system'
[patent_app_type] => utility
[patent_app_number] => 12/002122
[patent_app_country] => US
[patent_app_date] => 2007-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2173
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/802/07802086.pdf
[firstpage_image] =>[orig_patent_app_number] => 12002122
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/002122 | Method for recovering BIOS chip in a computer system | Dec 12, 2007 | Issued |
Array
(
[id] => 5442808
[patent_doc_number] => 20090094447
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-09
[patent_title] => 'Universal serial bus flash drive for booting computer and method for loading programs to the flash drive'
[patent_app_type] => utility
[patent_app_number] => 11/987819
[patent_app_country] => US
[patent_app_date] => 2007-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1678
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20090094447.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987819
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987819 | Universal serial bus flash drive for booting computer and method for loading programs to the flash drive | Dec 4, 2007 | Abandoned |
Array
(
[id] => 213370
[patent_doc_number] => 07624289
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-24
[patent_title] => 'Power network reconfiguration using MEM switches'
[patent_app_type] => utility
[patent_app_number] => 11/949129
[patent_app_country] => US
[patent_app_date] => 2007-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 4930
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/624/07624289.pdf
[firstpage_image] =>[orig_patent_app_number] => 11949129
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/949129 | Power network reconfiguration using MEM switches | Dec 2, 2007 | Issued |
Array
(
[id] => 4455031
[patent_doc_number] => 07966510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-21
[patent_title] => 'Dynamic frequency adjustment for interoperability of differential clock recovery methods'
[patent_app_type] => utility
[patent_app_number] => 11/987457
[patent_app_country] => US
[patent_app_date] => 2007-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3734
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/966/07966510.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987457
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987457 | Dynamic frequency adjustment for interoperability of differential clock recovery methods | Nov 29, 2007 | Issued |
Array
(
[id] => 305762
[patent_doc_number] => 07536571
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-19
[patent_title] => 'System and method to maintain data processing system operation in degraded system cooling condition'
[patent_app_type] => utility
[patent_app_number] => 11/947072
[patent_app_country] => US
[patent_app_date] => 2007-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 5637
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/536/07536571.pdf
[firstpage_image] =>[orig_patent_app_number] => 11947072
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/947072 | System and method to maintain data processing system operation in degraded system cooling condition | Nov 28, 2007 | Issued |
Array
(
[id] => 4830108
[patent_doc_number] => 20080126822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'Apparatus for aligning input data in semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/986917
[patent_app_country] => US
[patent_app_date] => 2007-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6991
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20080126822.pdf
[firstpage_image] =>[orig_patent_app_number] => 11986917
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/986917 | Apparatus for aligning input data in semiconductor memory device | Nov 26, 2007 | Issued |
Array
(
[id] => 58611
[patent_doc_number] => 07770044
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'Method and apparatus for waking up a circuit'
[patent_app_type] => utility
[patent_app_number] => 11/945146
[patent_app_country] => US
[patent_app_date] => 2007-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5540
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/770/07770044.pdf
[firstpage_image] =>[orig_patent_app_number] => 11945146
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/945146 | Method and apparatus for waking up a circuit | Nov 25, 2007 | Issued |
Array
(
[id] => 4830011
[patent_doc_number] => 20080126776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'Electronic apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/984952
[patent_app_country] => US
[patent_app_date] => 2007-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5449
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20080126776.pdf
[firstpage_image] =>[orig_patent_app_number] => 11984952
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/984952 | Electronic apparatus | Nov 25, 2007 | Abandoned |