Search

Susan Beth Mccormick Ewoldt

Examiner (ID: 13476, Phone: (571)272-0981 , Office: P/1661 )

Most Active Art Unit
1661
Art Unit(s)
1661, 1654, 1655, 1649
Total Applications
4273
Issued Applications
3965
Pending Applications
37
Abandoned Applications
283

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18054053 [patent_doc_number] => 11527445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Semiconductor devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/007555 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007555
Semiconductor devices and methods of manufacturing thereof Aug 30, 2020 Issued
Array ( [id] => 19488852 [patent_doc_number] => 12108595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Integrated fuse in self-aligned gate endcap for FinFET architectures and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/001525 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 35 [patent_no_of_words] => 14102 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001525
Integrated fuse in self-aligned gate endcap for FinFET architectures and methods of fabrication Aug 23, 2020 Issued
Array ( [id] => 18447062 [patent_doc_number] => 11682638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Semiconductor structure having multiple dielectric waveguide channels and method for forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/998854 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998854
Semiconductor structure having multiple dielectric waveguide channels and method for forming semiconductor structure Aug 19, 2020 Issued
Array ( [id] => 16487822 [patent_doc_number] => 20200381431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => INTEGRATED CIRCUIT STRUCTURE WITH SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/995941 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995941
Integrated circuit structure with semiconductor devices and method of fabricating the same Aug 17, 2020 Issued
Array ( [id] => 18073878 [patent_doc_number] => 11532720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/996094 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 10538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996094 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/996094
Semiconductor device and manufacturing method thereof Aug 17, 2020 Issued
Array ( [id] => 17417289 [patent_doc_number] => 20220052193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SINGLE DIFFUSION BREAKS INCLUDING STACKED DIELECTRIC LAYERS [patent_app_type] => utility [patent_app_number] => 16/994915 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994915 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994915
Single diffusion breaks including stacked dielectric layers Aug 16, 2020 Issued
Array ( [id] => 16487912 [patent_doc_number] => 20200381521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => DEVICES WITH LOWER RESISTANCE AND IMPROVED BREAKDOWN AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 16/995397 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995397 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995397
Devices with lower resistance and improved breakdown and method for producing the same Aug 16, 2020 Issued
Array ( [id] => 17188785 [patent_doc_number] => 20210335670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => FORMING ISOLATION REGIONS FOR SEPARATING FINS AND GATE STACKS [patent_app_type] => utility [patent_app_number] => 16/933386 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933386
Forming isolation regions for separating fins and gate stacks Jul 19, 2020 Issued
Array ( [id] => 17978802 [patent_doc_number] => 11495677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/926258 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926258 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926258
Semiconductor devices and methods of manufacturing thereof Jul 9, 2020 Issued
Array ( [id] => 16402613 [patent_doc_number] => 20200343471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/924439 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924439
Display device Jul 8, 2020 Issued
Array ( [id] => 18263176 [patent_doc_number] => 11610885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Method for forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 16/924541 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924541 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924541
Method for forming semiconductor structure Jul 8, 2020 Issued
Array ( [id] => 19213643 [patent_doc_number] => 12002715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 16/923348 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 9839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923348 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923348
Semiconductor device and method Jul 7, 2020 Issued
Array ( [id] => 16394654 [patent_doc_number] => 20200335595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/921187 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921187
Structure and formation method of semiconductor device structure with gate structure Jul 5, 2020 Issued
Array ( [id] => 16379348 [patent_doc_number] => 20200328191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => STACKED PACKAGE STRUCTURE AND STACKED PACKAGING METHOD FOR CHIP [patent_app_type] => utility [patent_app_number] => 16/913096 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913096 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913096
Stacked package structure and stacked packaging method for chip Jun 25, 2020 Issued
Array ( [id] => 17277930 [patent_doc_number] => 20210384128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/909968 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909968
Semiconductor device and manufacturing method thereof Jun 22, 2020 Issued
Array ( [id] => 18317650 [patent_doc_number] => 11631736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Epitaxial source/drain feature with enlarged lower section interfacing with backside via [patent_app_type] => utility [patent_app_number] => 16/901631 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 80 [patent_no_of_words] => 11926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901631
Epitaxial source/drain feature with enlarged lower section interfacing with backside via Jun 14, 2020 Issued
Array ( [id] => 18721583 [patent_doc_number] => 11798940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/897167 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 11614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/897167
Semiconductor device Jun 8, 2020 Issued
Array ( [id] => 16904939 [patent_doc_number] => 20210183855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/895795 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895795
Semiconductor structure and method for forming the same Jun 7, 2020 Issued
Array ( [id] => 17070631 [patent_doc_number] => 20210272848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => Cut EPI Process and Structures [patent_app_type] => utility [patent_app_number] => 16/887273 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887273
Cut EPI process and structures May 28, 2020 Issued
Array ( [id] => 17262879 [patent_doc_number] => 20210375864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => REDUCTION OF GATE-DRAIN CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/888537 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888537
Reduction of gate-drain capacitance May 28, 2020 Issued
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