
Susan Beth Mccormick Ewoldt
Examiner (ID: 13476, Phone: (571)272-0981 , Office: P/1661 )
| Most Active Art Unit | 1661 |
| Art Unit(s) | 1661, 1654, 1655, 1649 |
| Total Applications | 4273 |
| Issued Applications | 3965 |
| Pending Applications | 37 |
| Abandoned Applications | 283 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19007854
[patent_doc_number] => 20240071925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => FET SUBSTRATE TRIMMING WITH IMPROVED VIA PLACEMENT
[patent_app_type] => utility
[patent_app_number] => 17/898765
[patent_app_country] => US
[patent_app_date] => 2022-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6703
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898765
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/898765 | FET SUBSTRATE TRIMMING WITH IMPROVED VIA PLACEMENT | Aug 29, 2022 | Pending |
Array
(
[id] => 20229344
[patent_doc_number] => 12418000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Stacked package structure and stacked packaging method for chip
[patent_app_type] => utility
[patent_app_number] => 17/897450
[patent_app_country] => US
[patent_app_date] => 2022-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897450
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/897450 | Stacked package structure and stacked packaging method for chip | Aug 28, 2022 | Issued |
Array
(
[id] => 18040053
[patent_doc_number] => 20220384270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => Semiconductor Device and Method
[patent_app_type] => utility
[patent_app_number] => 17/818785
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818785
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/818785 | Semiconductor Device and Method | Aug 9, 2022 | Pending |
Array
(
[id] => 18059326
[patent_doc_number] => 20220390412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-08
[patent_title] => SEMICONDUCTOR BIOSENSOR
[patent_app_type] => utility
[patent_app_number] => 17/818175
[patent_app_country] => US
[patent_app_date] => 2022-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8706
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818175
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/818175 | Semiconductor biosensor | Aug 7, 2022 | Issued |
Array
(
[id] => 20276417
[patent_doc_number] => 12446206
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Three-dimensional semiconductor structure and formation method thereof
[patent_app_type] => utility
[patent_app_number] => 17/878053
[patent_app_country] => US
[patent_app_date] => 2022-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 1216
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 326
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878053
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/878053 | Three-dimensional semiconductor structure and formation method thereof | Jul 31, 2022 | Issued |
Array
(
[id] => 18008696
[patent_doc_number] => 20220367463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => REDUCTION OF GATE-DRAIN CAPACITANCE
[patent_app_type] => utility
[patent_app_number] => 17/874478
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11471
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874478
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874478 | REDUCTION OF GATE-DRAIN CAPACITANCE | Jul 26, 2022 | Pending |
Array
(
[id] => 18008510
[patent_doc_number] => 20220367277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => CUT EPI PROCESS AND STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/815302
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9538
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815302
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/815302 | Cut EPI process and structures | Jul 26, 2022 | Issued |
Array
(
[id] => 19796424
[patent_doc_number] => 12237396
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-25
[patent_title] => P-metal gate first gate replacement process for multigate devices
[patent_app_type] => utility
[patent_app_number] => 17/874031
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 90
[patent_no_of_words] => 15672
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874031
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874031 | P-metal gate first gate replacement process for multigate devices | Jul 25, 2022 | Issued |
Array
(
[id] => 17993663
[patent_doc_number] => 20220359700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/873203
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10488
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873203
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873203 | Semiconductor device and manufacturing method thereof | Jul 25, 2022 | Issued |
Array
(
[id] => 19796433
[patent_doc_number] => 12237405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-25
[patent_title] => Semiconductor devices and methods of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 17/873832
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9891
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873832
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873832 | Semiconductor devices and methods of manufacturing thereof | Jul 25, 2022 | Issued |
Array
(
[id] => 19765903
[patent_doc_number] => 12224204
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Semiconductor device and method
[patent_app_type] => utility
[patent_app_number] => 17/873353
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 59
[patent_no_of_words] => 13674
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873353
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873353 | Semiconductor device and method | Jul 25, 2022 | Issued |
Array
(
[id] => 17993501
[patent_doc_number] => 20220359538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => MEMORY DEVICE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/874045
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11059
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874045
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874045 | Memory device and method for forming the same | Jul 25, 2022 | Issued |
Array
(
[id] => 19906469
[patent_doc_number] => 12283485
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-22
[patent_title] => Cut metal gate refill with void
[patent_app_type] => utility
[patent_app_number] => 17/872623
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 49
[patent_figures_cnt] => 56
[patent_no_of_words] => 6865
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872623
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/872623 | Cut metal gate refill with void | Jul 24, 2022 | Issued |
Array
(
[id] => 17993685
[patent_doc_number] => 20220359722
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => Fin-End Gate Structures and Method Forming Same
[patent_app_type] => utility
[patent_app_number] => 17/814779
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7933
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814779
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814779 | Fin-end gate structures and method forming same | Jul 24, 2022 | Issued |
Array
(
[id] => 17993577
[patent_doc_number] => 20220359614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => MAGNETIC TUNNEL JUNCTION STRUCTURES AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 17/870695
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7369
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870695
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870695 | Magnetic tunnel junction structures and related methods | Jul 20, 2022 | Issued |
Array
(
[id] => 19733842
[patent_doc_number] => 12211844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 17/870133
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 88
[patent_no_of_words] => 15341
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870133
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/870133 | Semiconductor structure | Jul 20, 2022 | Issued |
Array
(
[id] => 17993269
[patent_doc_number] => 20220359306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/869995
[patent_app_country] => US
[patent_app_date] => 2022-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10851
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869995
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/869995 | Semiconductor devices and methods of manufacturing thereof | Jul 20, 2022 | Issued |
Array
(
[id] => 17993262
[patent_doc_number] => 20220359299
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => Forming Isolation Regions for Separating Fins and Gate Stacks
[patent_app_type] => utility
[patent_app_number] => 17/813850
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7057
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813850
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/813850 | Forming isolation regions for separating fins and gate stacks | Jul 19, 2022 | Issued |
Array
(
[id] => 19328968
[patent_doc_number] => 12046660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-23
[patent_title] => Non-conformal capping layer and method forming same
[patent_app_type] => utility
[patent_app_number] => 17/813793
[patent_app_country] => US
[patent_app_date] => 2022-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 29
[patent_no_of_words] => 10006
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813793
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/813793 | Non-conformal capping layer and method forming same | Jul 19, 2022 | Issued |
Array
(
[id] => 18230807
[patent_doc_number] => 20230069801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => Metal Gate Structure of High-Voltage Device and Method for Making the Same
[patent_app_type] => utility
[patent_app_number] => 17/848531
[patent_app_country] => US
[patent_app_date] => 2022-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2291
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848531
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/848531 | Metal Gate Structure of High-Voltage Device and Method for Making the Same | Jun 23, 2022 | Pending |