Search

Susan Dadio

Examiner (ID: 11306)

Most Active Art Unit
1808
Art Unit(s)
1808, 1651
Total Applications
189
Issued Applications
98
Pending Applications
19
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 934021 [patent_doc_number] => 06977216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Method for forming metal wire in semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/878316 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2738 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977216.pdf [firstpage_image] =>[orig_patent_app_number] => 10878316 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878316
Method for forming metal wire in semiconductor device Jun 28, 2004 Issued
Array ( [id] => 975506 [patent_doc_number] => 06933231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-23 [patent_title] => 'Methods of forming conductive interconnects, and methods of depositing nickel' [patent_app_type] => utility [patent_app_number] => 10/879366 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3297 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933231.pdf [firstpage_image] =>[orig_patent_app_number] => 10879366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/879366
Methods of forming conductive interconnects, and methods of depositing nickel Jun 27, 2004 Issued
Array ( [id] => 7097971 [patent_doc_number] => 20050130430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method for chemical mechanical polishing for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/876395 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1108 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130430.pdf [firstpage_image] =>[orig_patent_app_number] => 10876395 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876395
Method for chemical mechanical polishing for fabricating semiconductor device Jun 24, 2004 Issued
Array ( [id] => 7178722 [patent_doc_number] => 20050124103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method for manufacturing NAND flash device' [patent_app_type] => utility [patent_app_number] => 10/876065 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3534 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20050124103.pdf [firstpage_image] =>[orig_patent_app_number] => 10876065 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876065
Method for manufacturing NAND flash device Jun 23, 2004 Issued
Array ( [id] => 634073 [patent_doc_number] => 07129129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Vertical device with optimal trench shape' [patent_app_type] => utility [patent_app_number] => 10/708861 [patent_app_country] => US [patent_app_date] => 2004-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 3366 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129129.pdf [firstpage_image] =>[orig_patent_app_number] => 10708861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708861
Vertical device with optimal trench shape Mar 28, 2004 Issued
Array ( [id] => 985477 [patent_doc_number] => 06924205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Collar formation using selective SiGe/Si etch' [patent_app_type] => utility [patent_app_number] => 10/770278 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4391 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924205.pdf [firstpage_image] =>[orig_patent_app_number] => 10770278 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770278
Collar formation using selective SiGe/Si etch Feb 1, 2004 Issued
Array ( [id] => 931121 [patent_doc_number] => 06979625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Copper interconnects with metal capping layer and selective copper alloys' [patent_app_type] => utility [patent_app_number] => 10/704595 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5002 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979625.pdf [firstpage_image] =>[orig_patent_app_number] => 10704595 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/704595
Copper interconnects with metal capping layer and selective copper alloys Nov 11, 2003 Issued
Array ( [id] => 7622059 [patent_doc_number] => 06977442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Semiconductor device structure' [patent_app_type] => utility [patent_app_number] => 10/705306 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 40 [patent_no_of_words] => 14374 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977442.pdf [firstpage_image] =>[orig_patent_app_number] => 10705306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705306
Semiconductor device structure Nov 11, 2003 Issued
Array ( [id] => 934034 [patent_doc_number] => 06977229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Manufacturing method for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/460155 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6703 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977229.pdf [firstpage_image] =>[orig_patent_app_number] => 10460155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460155
Manufacturing method for semiconductor devices Jun 12, 2003 Issued
Array ( [id] => 7264061 [patent_doc_number] => 20040241939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'METHOD OF FORMING A COLLAR USING SELECTIVE SiGe/AMORPHOUS Si ETCH' [patent_app_type] => new [patent_app_number] => 10/250046 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241939.pdf [firstpage_image] =>[orig_patent_app_number] => 10250046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/250046
Method of forming a collar using selective SiGe/Amorphous Si Etch May 29, 2003 Issued
Array ( [id] => 1040572 [patent_doc_number] => 06869870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'High performance system-on-chip discrete components using post passivation process' [patent_app_type] => utility [patent_app_number] => 10/445560 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 40 [patent_no_of_words] => 8784 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869870.pdf [firstpage_image] =>[orig_patent_app_number] => 10445560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445560
High performance system-on-chip discrete components using post passivation process May 26, 2003 Issued
Array ( [id] => 785208 [patent_doc_number] => 06989302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for fabricating a p-type shallow junction using diatomic arsenic' [patent_app_type] => utility [patent_app_number] => 10/429796 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3797 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989302.pdf [firstpage_image] =>[orig_patent_app_number] => 10429796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/429796
Method for fabricating a p-type shallow junction using diatomic arsenic May 4, 2003 Issued
Array ( [id] => 931105 [patent_doc_number] => 06979609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks' [patent_app_type] => utility [patent_app_number] => 10/426221 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3866 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979609.pdf [firstpage_image] =>[orig_patent_app_number] => 10426221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426221
Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks Apr 29, 2003 Issued
Array ( [id] => 7406472 [patent_doc_number] => 20040175870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR' [patent_app_type] => new [patent_app_number] => 10/249585 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2277 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175870.pdf [firstpage_image] =>[orig_patent_app_number] => 10249585 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249585
METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR Apr 21, 2003 Abandoned
Array ( [id] => 7383641 [patent_doc_number] => 20040029370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Memory transistor and methods' [patent_app_type] => new [patent_app_number] => 10/393129 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20040029370.pdf [firstpage_image] =>[orig_patent_app_number] => 10393129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/393129
Memory transistor structure Mar 18, 2003 Issued
Array ( [id] => 1037494 [patent_doc_number] => 06872643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Implant damage removal by laser thermal annealing' [patent_app_type] => utility [patent_app_number] => 10/378885 [patent_app_country] => US [patent_app_date] => 2003-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2628 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872643.pdf [firstpage_image] =>[orig_patent_app_number] => 10378885 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/378885
Implant damage removal by laser thermal annealing Mar 4, 2003 Issued
Array ( [id] => 7629836 [patent_doc_number] => 06818520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method for controlling critical dimension in an HBT emitter' [patent_app_type] => B1 [patent_app_number] => 10/364550 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4020 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818520.pdf [firstpage_image] =>[orig_patent_app_number] => 10364550 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364550
Method for controlling critical dimension in an HBT emitter Feb 9, 2003 Issued
Array ( [id] => 773437 [patent_doc_number] => 07001813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Layers of group III-nitride semiconductor made by processes with multi-step epitaxial growths' [patent_app_type] => utility [patent_app_number] => 10/349007 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5828 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/001/07001813.pdf [firstpage_image] =>[orig_patent_app_number] => 10349007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349007
Layers of group III-nitride semiconductor made by processes with multi-step epitaxial growths Jan 21, 2003 Issued
Array ( [id] => 1128147 [patent_doc_number] => 06791107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Silicon on insulator phase change memory' [patent_app_type] => B2 [patent_app_number] => 10/336171 [patent_app_country] => US [patent_app_date] => 2003-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4861 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791107.pdf [firstpage_image] =>[orig_patent_app_number] => 10336171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336171
Silicon on insulator phase change memory Jan 2, 2003 Issued
Array ( [id] => 996543 [patent_doc_number] => 06913982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Method of fabricating a probe of a scanning probe microscope (SPM) having a field-effect transistor channel' [patent_app_type] => utility [patent_app_number] => 10/336068 [patent_app_country] => US [patent_app_date] => 2003-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3997 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/913/06913982.pdf [firstpage_image] =>[orig_patent_app_number] => 10336068 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336068
Method of fabricating a probe of a scanning probe microscope (SPM) having a field-effect transistor channel Jan 1, 2003 Issued
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