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Susan Dadio

Examiner (ID: 11306)

Most Active Art Unit
1808
Art Unit(s)
1808, 1651
Total Applications
189
Issued Applications
98
Pending Applications
19
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6986871 [patent_doc_number] => 20010036703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method of manufacturing capacitor of semiconductor device' [patent_app_type] => new [patent_app_number] => 09/745426 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3022 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036703.pdf [firstpage_image] =>[orig_patent_app_number] => 09745426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745426
Method of manufacturing capacitor of semiconductor device using an amorphous TaON Dec 25, 2000 Issued
Array ( [id] => 6876684 [patent_doc_number] => 20010006837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Method for manufacturing a semiconductor memory device using hemispherical grain silicon' [patent_app_type] => new-utility [patent_app_number] => 09/735626 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1564 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006837.pdf [firstpage_image] =>[orig_patent_app_number] => 09735626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735626
Method for manufacturing a semiconductor memory device using hemispherical grain silicon Dec 13, 2000 Issued
Array ( [id] => 6838892 [patent_doc_number] => 20030036232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory.' [patent_app_type] => new [patent_app_number] => 09/737363 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6437 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20030036232.pdf [firstpage_image] =>[orig_patent_app_number] => 09737363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737363
Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory Dec 13, 2000 Issued
Array ( [id] => 1590711 [patent_doc_number] => 06483131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'High density and high speed cell array architecture' [patent_app_type] => B1 [patent_app_number] => 09/738015 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2455 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483131.pdf [firstpage_image] =>[orig_patent_app_number] => 09738015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738015
High density and high speed cell array architecture Dec 13, 2000 Issued
Array ( [id] => 982235 [patent_doc_number] => 06927079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method for probing a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 09/731596 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5169 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927079.pdf [firstpage_image] =>[orig_patent_app_number] => 09731596 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731596
Method for probing a semiconductor wafer Dec 5, 2000 Issued
Array ( [id] => 1140087 [patent_doc_number] => 06772992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Memory cell structure integrated on semiconductor' [patent_app_type] => B1 [patent_app_number] => 09/701768 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2711 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772992.pdf [firstpage_image] =>[orig_patent_app_number] => 09701768 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/701768
Memory cell structure integrated on semiconductor Nov 29, 2000 Issued
Array ( [id] => 1503532 [patent_doc_number] => 06465321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method of forming a storage node in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/722505 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1526 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465321.pdf [firstpage_image] =>[orig_patent_app_number] => 09722505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722505
Method of forming a storage node in a semiconductor device Nov 27, 2000 Issued
Array ( [id] => 1446553 [patent_doc_number] => 06368910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of fabricating ruthenium-based contact plug for memory devices' [patent_app_type] => B1 [patent_app_number] => 09/721796 [patent_app_country] => US [patent_app_date] => 2000-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368910.pdf [firstpage_image] =>[orig_patent_app_number] => 09721796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/721796
Method of fabricating ruthenium-based contact plug for memory devices Nov 23, 2000 Issued
Array ( [id] => 1585502 [patent_doc_number] => 06358813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method for increasing the capacitance of a semiconductor capacitors' [patent_app_type] => B1 [patent_app_number] => 09/713766 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2935 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358813.pdf [firstpage_image] =>[orig_patent_app_number] => 09713766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713766
Method for increasing the capacitance of a semiconductor capacitors Nov 14, 2000 Issued
Array ( [id] => 1416072 [patent_doc_number] => 06509209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method of forming a metal-to-metal antifuse with non-conductive diffusion barrier' [patent_app_type] => B1 [patent_app_number] => 09/697706 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 7518 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509209.pdf [firstpage_image] =>[orig_patent_app_number] => 09697706 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697706
Method of forming a metal-to-metal antifuse with non-conductive diffusion barrier Oct 24, 2000 Issued
Array ( [id] => 1585498 [patent_doc_number] => 06358812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Methods of forming storage capacitors' [patent_app_type] => B1 [patent_app_number] => 09/692485 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 2773 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358812.pdf [firstpage_image] =>[orig_patent_app_number] => 09692485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/692485
Methods of forming storage capacitors Oct 17, 2000 Issued
Array ( [id] => 1462499 [patent_doc_number] => 06350653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Embedded DRAM on silicon-on-insulator substrate' [patent_app_type] => B1 [patent_app_number] => 09/689096 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2933 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350653.pdf [firstpage_image] =>[orig_patent_app_number] => 09689096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689096
Embedded DRAM on silicon-on-insulator substrate Oct 11, 2000 Issued
Array ( [id] => 1500422 [patent_doc_number] => 06486058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method of forming a photoresist pattern using WASOOM' [patent_app_type] => B1 [patent_app_number] => 09/679265 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486058.pdf [firstpage_image] =>[orig_patent_app_number] => 09679265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679265
Method of forming a photoresist pattern using WASOOM Oct 3, 2000 Issued
Array ( [id] => 1450001 [patent_doc_number] => 06455393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Air bridge/dielectric fill inductors' [patent_app_type] => B1 [patent_app_number] => 09/677456 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4158 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455393.pdf [firstpage_image] =>[orig_patent_app_number] => 09677456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677456
Air bridge/dielectric fill inductors Oct 1, 2000 Issued
Array ( [id] => 1474703 [patent_doc_number] => 06387822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Application of an ozonated DI water spray to resist residue removal processes' [patent_app_type] => B1 [patent_app_number] => 09/666576 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1811 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387822.pdf [firstpage_image] =>[orig_patent_app_number] => 09666576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666576
Application of an ozonated DI water spray to resist residue removal processes Sep 20, 2000 Issued
Array ( [id] => 1319347 [patent_doc_number] => 06608389 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Semiconductor device with stress relieving layer comprising circuit board and electronic instrument' [patent_app_type] => B1 [patent_app_number] => 09/666406 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 64 [patent_no_of_words] => 10354 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/608/06608389.pdf [firstpage_image] =>[orig_patent_app_number] => 09666406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666406
Semiconductor device with stress relieving layer comprising circuit board and electronic instrument Sep 19, 2000 Issued
Array ( [id] => 1446591 [patent_doc_number] => 06368932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method for producing diodes' [patent_app_type] => B1 [patent_app_number] => 09/600685 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2165 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368932.pdf [firstpage_image] =>[orig_patent_app_number] => 09600685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/600685
Method for producing diodes Sep 5, 2000 Issued
Array ( [id] => 1459421 [patent_doc_number] => 06391735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Container capacitor structure' [patent_app_type] => B1 [patent_app_number] => 09/653226 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 7143 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391735.pdf [firstpage_image] =>[orig_patent_app_number] => 09653226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653226
Container capacitor structure Aug 30, 2000 Issued
Array ( [id] => 1549716 [patent_doc_number] => 06346455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method to form a corrugated structure for enhanced capacitance' [patent_app_type] => B1 [patent_app_number] => 09/651946 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2076 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346455.pdf [firstpage_image] =>[orig_patent_app_number] => 09651946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651946
Method to form a corrugated structure for enhanced capacitance Aug 30, 2000 Issued
Array ( [id] => 1414419 [patent_doc_number] => 06521507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Selective deposition of undoped silicon film seeded in chlorine and hydride gas for a stacked capacitor' [patent_app_type] => B1 [patent_app_number] => 09/653086 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3235 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521507.pdf [firstpage_image] =>[orig_patent_app_number] => 09653086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653086
Selective deposition of undoped silicon film seeded in chlorine and hydride gas for a stacked capacitor Aug 30, 2000 Issued
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