Search

Susan Dadio

Examiner (ID: 11306)

Most Active Art Unit
1808
Art Unit(s)
1808, 1651
Total Applications
189
Issued Applications
98
Pending Applications
19
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1545219 [patent_doc_number] => 06444537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method of preparing a capacitor on integrated circuit device containing isolated dielectric material' [patent_app_type] => B1 [patent_app_number] => 09/650215 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4265 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444537.pdf [firstpage_image] =>[orig_patent_app_number] => 09650215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650215
Method of preparing a capacitor on integrated circuit device containing isolated dielectric material Aug 28, 2000 Issued
09/649251 Method for fabricating an npn transistor in a bicmos technology Aug 27, 2000 Abandoned
Array ( [id] => 1520738 [patent_doc_number] => 06413862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Use of palladium in IC manufacturing' [patent_app_type] => B1 [patent_app_number] => 09/645947 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3732 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413862.pdf [firstpage_image] =>[orig_patent_app_number] => 09645947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645947
Use of palladium in IC manufacturing Aug 24, 2000 Issued
Array ( [id] => 4405266 [patent_doc_number] => 06232168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Memory circuitry and method of forming memory circuitry' [patent_app_type] => 1 [patent_app_number] => 9/648585 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2633 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232168.pdf [firstpage_image] =>[orig_patent_app_number] => 648585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648585
Memory circuitry and method of forming memory circuitry Aug 24, 2000 Issued
Array ( [id] => 1490140 [patent_doc_number] => 06417045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity' [patent_app_type] => B1 [patent_app_number] => 09/642586 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 71 [patent_no_of_words] => 19169 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417045.pdf [firstpage_image] =>[orig_patent_app_number] => 09642586 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642586
Method of manufacturing a semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity Aug 21, 2000 Issued
Array ( [id] => 1594510 [patent_doc_number] => 06383906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption' [patent_app_type] => B1 [patent_app_number] => 09/641436 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3483 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383906.pdf [firstpage_image] =>[orig_patent_app_number] => 09641436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/641436
Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption Aug 17, 2000 Issued
Array ( [id] => 1390201 [patent_doc_number] => 06544858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method for treating silicon-containing polymer layers with plasma or electromagnetic radiation' [patent_app_type] => B1 [patent_app_number] => 09/601086 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2761 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544858.pdf [firstpage_image] =>[orig_patent_app_number] => 09601086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/601086
Method for treating silicon-containing polymer layers with plasma or electromagnetic radiation Aug 17, 2000 Issued
Array ( [id] => 4329112 [patent_doc_number] => 06313003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Fabrication process for metal-insulator-metal capacitor with low gate resistance' [patent_app_type] => 1 [patent_app_number] => 9/640545 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 7255 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313003.pdf [firstpage_image] =>[orig_patent_app_number] => 640545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640545
Fabrication process for metal-insulator-metal capacitor with low gate resistance Aug 16, 2000 Issued
Array ( [id] => 1545275 [patent_doc_number] => 06444550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Laser tailoring retrograde channel profile in surfaces' [patent_app_type] => B1 [patent_app_number] => 09/640177 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2639 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444550.pdf [firstpage_image] =>[orig_patent_app_number] => 09640177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640177
Laser tailoring retrograde channel profile in surfaces Aug 16, 2000 Issued
Array ( [id] => 1565746 [patent_doc_number] => 06376305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method of forming DRAM circuitry, DRAM circuitry, method of forming a field emission device, and field emission device' [patent_app_type] => B1 [patent_app_number] => 09/641879 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376305.pdf [firstpage_image] =>[orig_patent_app_number] => 09641879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/641879
Method of forming DRAM circuitry, DRAM circuitry, method of forming a field emission device, and field emission device Aug 16, 2000 Issued
Array ( [id] => 1561111 [patent_doc_number] => 06362052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell' [patent_app_type] => B1 [patent_app_number] => 09/627567 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4448 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362052.pdf [firstpage_image] =>[orig_patent_app_number] => 09627567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627567
Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell Jul 27, 2000 Issued
Array ( [id] => 1563147 [patent_doc_number] => 06362524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Edge seal ring for copper damascene process and method for fabrication thereof' [patent_app_type] => B1 [patent_app_number] => 09/625367 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 3062 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362524.pdf [firstpage_image] =>[orig_patent_app_number] => 09625367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625367
Edge seal ring for copper damascene process and method for fabrication thereof Jul 25, 2000 Issued
Array ( [id] => 1494907 [patent_doc_number] => 06403436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/619337 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3819 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403436.pdf [firstpage_image] =>[orig_patent_app_number] => 09619337 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/619337
Semiconductor device and method of manufacturing the same Jul 18, 2000 Issued
Array ( [id] => 1523666 [patent_doc_number] => 06352896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method of manufacturing DRAM capacitor' [patent_app_type] => B1 [patent_app_number] => 09/618597 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 3264 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352896.pdf [firstpage_image] =>[orig_patent_app_number] => 09618597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618597
Method of manufacturing DRAM capacitor Jul 16, 2000 Issued
Array ( [id] => 1597098 [patent_doc_number] => 06384452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Electrostatic discharge protection device with monolithically formed resistor-capacitor portion' [patent_app_type] => B1 [patent_app_number] => 09/617687 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3123 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384452.pdf [firstpage_image] =>[orig_patent_app_number] => 09617687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/617687
Electrostatic discharge protection device with monolithically formed resistor-capacitor portion Jul 16, 2000 Issued
Array ( [id] => 1588730 [patent_doc_number] => 06482686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/615077 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 7411 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482686.pdf [firstpage_image] =>[orig_patent_app_number] => 09615077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/615077
Method for manufacturing a semiconductor device Jul 11, 2000 Issued
Array ( [id] => 1561809 [patent_doc_number] => 06437420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Semiconductor elements for semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/613227 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3686 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437420.pdf [firstpage_image] =>[orig_patent_app_number] => 09613227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613227
Semiconductor elements for semiconductor device Jul 9, 2000 Issued
Array ( [id] => 1406549 [patent_doc_number] => 06538283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer' [patent_app_type] => B1 [patent_app_number] => 09/611907 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2455 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538283.pdf [firstpage_image] =>[orig_patent_app_number] => 09611907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/611907
Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer Jul 6, 2000 Issued
Array ( [id] => 1474560 [patent_doc_number] => 06387773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for fabricating trenches having hallows along the trenches side wall for storage capacitors of DRAM semiconductor memories' [patent_app_type] => B1 [patent_app_number] => 09/607355 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2051 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387773.pdf [firstpage_image] =>[orig_patent_app_number] => 09607355 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607355
Method for fabricating trenches having hallows along the trenches side wall for storage capacitors of DRAM semiconductor memories Jun 29, 2000 Issued
Array ( [id] => 4365871 [patent_doc_number] => 06274424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for forming a capacitor electrode' [patent_app_type] => 1 [patent_app_number] => 9/602785 [patent_app_country] => US [patent_app_date] => 2000-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5290 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274424.pdf [firstpage_image] =>[orig_patent_app_number] => 602785 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/602785
Method for forming a capacitor electrode Jun 22, 2000 Issued
Menu