Search

Susan Dadio

Examiner (ID: 11306)

Most Active Art Unit
1808
Art Unit(s)
1808, 1651
Total Applications
189
Issued Applications
98
Pending Applications
19
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1553470 [patent_doc_number] => 06348374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure' [patent_app_type] => B1 [patent_app_number] => 09/597887 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 6489 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348374.pdf [firstpage_image] =>[orig_patent_app_number] => 09597887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597887
Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure Jun 18, 2000 Issued
Array ( [id] => 1435868 [patent_doc_number] => 06355511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method of providing a frontside contact to substrate of SOI device' [patent_app_type] => B1 [patent_app_number] => 09/597357 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2665 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355511.pdf [firstpage_image] =>[orig_patent_app_number] => 09597357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597357
Method of providing a frontside contact to substrate of SOI device Jun 15, 2000 Issued
Array ( [id] => 7643980 [patent_doc_number] => 06429058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method of forming fully self-aligned TFT improved process window' [patent_app_type] => B1 [patent_app_number] => 09/585767 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5247 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429058.pdf [firstpage_image] =>[orig_patent_app_number] => 09585767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585767
Method of forming fully self-aligned TFT improved process window Jun 1, 2000 Issued
Array ( [id] => 1559771 [patent_doc_number] => 06436786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/570545 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5459 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436786.pdf [firstpage_image] =>[orig_patent_app_number] => 09570545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570545
Method for fabricating a semiconductor device May 11, 2000 Issued
Array ( [id] => 1578247 [patent_doc_number] => 06448168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method for distributing a clock on the silicon backside of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/483573 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5556 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448168.pdf [firstpage_image] =>[orig_patent_app_number] => 09483573 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483573
Method for distributing a clock on the silicon backside of an integrated circuit Apr 13, 2000 Issued
Array ( [id] => 1566081 [patent_doc_number] => 06376373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/523985 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3230 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376373.pdf [firstpage_image] =>[orig_patent_app_number] => 09523985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523985
Method of manufacturing a semiconductor device Mar 12, 2000 Issued
Array ( [id] => 4365771 [patent_doc_number] => 06274417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method of forming a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/515836 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4881 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274417.pdf [firstpage_image] =>[orig_patent_app_number] => 515836 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515836
Method of forming a semiconductor device Feb 28, 2000 Issued
Array ( [id] => 1561119 [patent_doc_number] => 06362056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method of making alternative to dual gate oxide for MOSFETs' [patent_app_type] => B1 [patent_app_number] => 09/511567 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3534 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362056.pdf [firstpage_image] =>[orig_patent_app_number] => 09511567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511567
Method of making alternative to dual gate oxide for MOSFETs Feb 22, 2000 Issued
Array ( [id] => 4368520 [patent_doc_number] => 06287904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Two step mask process to eliminate gate end cap shortening' [patent_app_type] => 1 [patent_app_number] => 9/499047 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3294 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287904.pdf [firstpage_image] =>[orig_patent_app_number] => 499047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499047
Two step mask process to eliminate gate end cap shortening Feb 6, 2000 Issued
Array ( [id] => 4271277 [patent_doc_number] => 06323100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/460115 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 6598 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323100.pdf [firstpage_image] =>[orig_patent_app_number] => 460115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460115
Method for manufacturing a semiconductor device Dec 12, 1999 Issued
Array ( [id] => 4377060 [patent_doc_number] => 06303409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Methods for separating microcircuit dies from wafers' [patent_app_type] => 1 [patent_app_number] => 9/456466 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5089 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303409.pdf [firstpage_image] =>[orig_patent_app_number] => 456466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456466
Methods for separating microcircuit dies from wafers Dec 7, 1999 Abandoned
Array ( [id] => 4268145 [patent_doc_number] => 06322903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Package of integrated circuits and vertical integration' [patent_app_type] => 1 [patent_app_number] => 9/456225 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 6022 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/322/06322903.pdf [firstpage_image] =>[orig_patent_app_number] => 456225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456225
Package of integrated circuits and vertical integration Dec 5, 1999 Issued
Array ( [id] => 4269917 [patent_doc_number] => 06245633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Fabrication method for a double-side double-crown stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 9/454387 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2749 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245633.pdf [firstpage_image] =>[orig_patent_app_number] => 454387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454387
Fabrication method for a double-side double-crown stacked capacitor Dec 2, 1999 Issued
Array ( [id] => 4321757 [patent_doc_number] => 06331462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Manufacturing method of a semiconductor device for desired circuit patterns' [patent_app_type] => 1 [patent_app_number] => 9/453807 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 58 [patent_no_of_words] => 8890 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331462.pdf [firstpage_image] =>[orig_patent_app_number] => 453807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453807
Manufacturing method of a semiconductor device for desired circuit patterns Dec 2, 1999 Issued
Array ( [id] => 4270946 [patent_doc_number] => 06323079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/445087 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 7088 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323079.pdf [firstpage_image] =>[orig_patent_app_number] => 445087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/445087
Method for manufacturing a semiconductor device Dec 1, 1999 Issued
Array ( [id] => 4394528 [patent_doc_number] => 06297089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method of forming buried straps in DRAMs' [patent_app_type] => 1 [patent_app_number] => 9/447630 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4142 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297089.pdf [firstpage_image] =>[orig_patent_app_number] => 447630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447630
Method of forming buried straps in DRAMs Nov 22, 1999 Issued
Array ( [id] => 1550301 [patent_doc_number] => 06399440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method to reduce the node contact resistance' [patent_app_type] => B1 [patent_app_number] => 09/447007 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2427 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399440.pdf [firstpage_image] =>[orig_patent_app_number] => 09447007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447007
Method to reduce the node contact resistance Nov 21, 1999 Issued
Array ( [id] => 1399335 [patent_doc_number] => 06537906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Methods for fabricating semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/438166 [patent_app_country] => US [patent_app_date] => 1999-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5854 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537906.pdf [firstpage_image] =>[orig_patent_app_number] => 09438166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438166
Methods for fabricating semiconductor devices Nov 10, 1999 Issued
Array ( [id] => 4318500 [patent_doc_number] => 06248622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Fabrication method for ultra short channel device comprising self-aligned landing pad' [patent_app_type] => 1 [patent_app_number] => 9/427880 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2959 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248622.pdf [firstpage_image] =>[orig_patent_app_number] => 427880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427880
Fabrication method for ultra short channel device comprising self-aligned landing pad Oct 26, 1999 Issued
Array ( [id] => 4368646 [patent_doc_number] => 06287913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Double polysilicon process for providing single chip high performance logic and compact embedded memory structure' [patent_app_type] => 1 [patent_app_number] => 9/427506 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4813 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287913.pdf [firstpage_image] =>[orig_patent_app_number] => 427506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427506
Double polysilicon process for providing single chip high performance logic and compact embedded memory structure Oct 25, 1999 Issued
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