Susan Dadio

Array ( [id] => 1450034 [patent_doc_number] => 06455406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Semiconductor processing method of forming a conductive connection through WxSiyNz material with specific contact opening etching' [patent_app_type] => B1 [patent_app_number] => 09/997735 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2738 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455406.pdf [firstpage_image] =>[orig_patent_app_number] => 09997735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6594296 [patent_doc_number] => 20020063307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Structure for a semiconductor resistive element, particularly for high voltage applications and respective manufacturing process' [patent_app_type] => new [patent_app_number] => 09/991555 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2522 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20020063307.pdf [firstpage_image] =>[orig_patent_app_number] => 09991555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1399338 [patent_doc_number] => 06545306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor memory device with a connector for a lower electrode or a bit line' [patent_app_type] => B2 [patent_app_number] => 09/988679 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 9575 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545306.pdf [firstpage_image] =>[orig_patent_app_number] => 09988679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1419238 [patent_doc_number] => 06506660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Semiconductor with nanoscale features' [patent_app_type] => B2 [patent_app_number] => 10/008092 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2957 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506660.pdf [firstpage_image] =>[orig_patent_app_number] => 10008092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416812 [patent_doc_number] => 06528838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Damascene MIM capacitor with a curvilinear surface structure' [patent_app_type] => B1 [patent_app_number] => 10/012296 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 3950 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528838.pdf [firstpage_image] =>[orig_patent_app_number] => 10012296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6359092 [patent_doc_number] => 20020058372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Method for forming a gate in a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/036279 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3466 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20020058372.pdf [firstpage_image] =>[orig_patent_app_number] => 10036279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634832 [patent_doc_number] => 06656786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'MIM process for logic-based embedded RAM having front end manufacturing operation' [patent_app_type] => B2 [patent_app_number] => 10/000896 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3569 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656786.pdf [firstpage_image] =>[orig_patent_app_number] => 10000896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6618221 [patent_doc_number] => 20020064913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Embedded dram on silicon-on-insulator substrate' [patent_app_type] => new [patent_app_number] => 10/000198 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2971 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064913.pdf [firstpage_image] =>[orig_patent_app_number] => 10000198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5825896 [patent_doc_number] => 20020066924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'High voltage power MOSFET having low on-resistance' [patent_app_type] => new [patent_app_number] => 10/021466 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2747 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066924.pdf [firstpage_image] =>[orig_patent_app_number] => 10021466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6474070 [patent_doc_number] => 20020022315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Self-aligned damascene interconnect' [patent_app_type] => new [patent_app_number] => 09/982207 [patent_app_country] => US [patent_app_date] => 2001-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3304 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20020022315.pdf [firstpage_image] =>[orig_patent_app_number] => 09982207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6033005 [patent_doc_number] => 20020019109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Semiconductor memory device production method' [patent_app_type] => new [patent_app_number] => 09/977228 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2988 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019109.pdf [firstpage_image] =>[orig_patent_app_number] => 09977228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1398068 [patent_doc_number] => 06537840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Manufacturing process of thin film transistor liquid crystal display with one mask' [patent_app_type] => B2 [patent_app_number] => 09/976771 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 2539 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537840.pdf [firstpage_image] =>[orig_patent_app_number] => 09976771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5888703 [patent_doc_number] => 20020013032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Process to fabricate a novel source-drain extension' [patent_app_type] => new [patent_app_number] => 09/972629 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3731 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013032.pdf [firstpage_image] =>[orig_patent_app_number] => 09972629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418315 [patent_doc_number] => 06514839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations' [patent_app_type] => B1 [patent_app_number] => 09/970825 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 49 [patent_no_of_words] => 9102 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514839.pdf [firstpage_image] =>[orig_patent_app_number] => 09970825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478094 [patent_doc_number] => 06451662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method of forming low-leakage on-chip capacitor' [patent_app_type] => B1 [patent_app_number] => 09/970635 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4999 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451662.pdf [firstpage_image] =>[orig_patent_app_number] => 09970635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6618363 [patent_doc_number] => 20020064922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'High performance system-on-chip using post passivation process' [patent_app_type] => new [patent_app_number] => 09/970005 [patent_app_country] => US [patent_app_date] => 2001-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8761 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064922.pdf [firstpage_image] =>[orig_patent_app_number] => 09970005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1494867 [patent_doc_number] => 06403424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for forming self-aligned mask read only memory by dual damascene trenches' [patent_app_type] => B1 [patent_app_number] => 09/967955 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 2291 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403424.pdf [firstpage_image] =>[orig_patent_app_number] => 09967955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5870702 [patent_doc_number] => 20020047204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 09/967720 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5489 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047204.pdf [firstpage_image] =>[orig_patent_app_number] => 09967720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6095883 [patent_doc_number] => 20020052077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'LOW-LEAKAGE DRAM STRUCTURES USING SELECTIVE SILICON EPITAXIAL GROWTH (SEG) ON AN INSULATING LAYER' [patent_app_type] => new [patent_app_number] => 09/963411 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4066 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20020052077.pdf [firstpage_image] =>[orig_patent_app_number] => 09963411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5936230 [patent_doc_number] => 20020061660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'SOI annealing method and SOI manufacturing method' [patent_app_type] => new [patent_app_number] => 09/963448 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7372 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20020061660.pdf [firstpage_image] =>[orig_patent_app_number] => 09963448 [rel_patent_id] =>[rel_patent_doc_number] =>)