
Susan J Lucas
Examiner (ID: 6780)
| Most Active Art Unit | 2901 |
| Art Unit(s) | 2911, 2900, 2901, 3105, 2899 |
| Total Applications | 6776 |
| Issued Applications | 6671 |
| Pending Applications | 1 |
| Abandoned Applications | 104 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19560001
[patent_doc_number] => 20240371793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => SEMICONDUCTOR DEVICE HAVING A BACKSIDE METALLIZATION LAYER AND A PROTECTION LAYER
[patent_app_type] => utility
[patent_app_number] => 18/774282
[patent_app_country] => US
[patent_app_date] => 2024-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774282
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/774282 | SEMICONDUCTOR DEVICE HAVING A BACKSIDE METALLIZATION LAYER AND A PROTECTION LAYER | Jul 15, 2024 | Pending |
Array
(
[id] => 19546527
[patent_doc_number] => 20240363563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => PASSIVATION STRUCTURE WITH INCREASED THICKNESS FOR METAL PADS
[patent_app_type] => utility
[patent_app_number] => 18/766279
[patent_app_country] => US
[patent_app_date] => 2024-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7451
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766279
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/766279 | PASSIVATION STRUCTURE WITH INCREASED THICKNESS FOR METAL PADS | Jul 7, 2024 | Pending |
Array
(
[id] => 19453054
[patent_doc_number] => 20240313184
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => LIGHT EMITTING DIODE
[patent_app_type] => utility
[patent_app_number] => 18/671619
[patent_app_country] => US
[patent_app_date] => 2024-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25056
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671619
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/671619 | Light emitting diode | May 21, 2024 | Issued |
Array
(
[id] => 19436226
[patent_doc_number] => 20240304724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => METHOD OF FORMING SOURCE/DRAIN EPITAXIAL STACKS
[patent_app_type] => utility
[patent_app_number] => 18/662615
[patent_app_country] => US
[patent_app_date] => 2024-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6532
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662615
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/662615 | METHOD OF FORMING SOURCE/DRAIN EPITAXIAL STACKS | May 12, 2024 | Pending |
Array
(
[id] => 19765883
[patent_doc_number] => 12224184
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Methods for registration of circuit dies and electrical interconnects
[patent_app_type] => utility
[patent_app_number] => 18/652529
[patent_app_country] => US
[patent_app_date] => 2024-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 6740
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652529
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/652529 | Methods for registration of circuit dies and electrical interconnects | Apr 30, 2024 | Issued |
Array
(
[id] => 19964915
[patent_doc_number] => 12334435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-17
[patent_title] => Middle-of-line interconnect structure and manufacturing method
[patent_app_type] => utility
[patent_app_number] => 18/650166
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 2356
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650166
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/650166 | Middle-of-line interconnect structure and manufacturing method | Apr 29, 2024 | Issued |
Array
(
[id] => 19943661
[patent_doc_number] => 12315797
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Semiconductor substrate structure and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/614472
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 2972
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614472
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614472 | Semiconductor substrate structure and method of manufacturing the same | Mar 21, 2024 | Issued |
Array
(
[id] => 19858260
[patent_doc_number] => 12261111
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Memory devices and related methods of forming a memory device
[patent_app_type] => utility
[patent_app_number] => 18/600146
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 14288
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600146
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/600146 | Memory devices and related methods of forming a memory device | Mar 7, 2024 | Issued |
Array
(
[id] => 19384575
[patent_doc_number] => 20240274445
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => HYBRID PANEL METHOD OF MANUFACTURING ELECTRONIC DEVICES AND ELECTRONIC DEVICES MANUFACTURED THEREBY
[patent_app_type] => utility
[patent_app_number] => 18/587291
[patent_app_country] => US
[patent_app_date] => 2024-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20086
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587291
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/587291 | HYBRID PANEL METHOD OF MANUFACTURING ELECTRONIC DEVICES AND ELECTRONIC DEVICES MANUFACTURED THEREBY | Feb 25, 2024 | Pending |
Array
(
[id] => 19237291
[patent_doc_number] => 20240194486
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => BACKSIDE AND SIDEWALL METALLIZATION OF SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/444826
[patent_app_country] => US
[patent_app_date] => 2024-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3400
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444826
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/444826 | BACKSIDE AND SIDEWALL METALLIZATION OF SEMICONDUCTOR DEVICES | Feb 18, 2024 | Pending |
Array
(
[id] => 19306080
[patent_doc_number] => 20240234660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/433367
[patent_app_country] => US
[patent_app_date] => 2024-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9976
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433367
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/433367 | Light-emitting device and manufacturing method thereof | Feb 4, 2024 | Issued |
Array
(
[id] => 20305395
[patent_doc_number] => 12451394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Methods of manufacturing semiconductor chip including crack propagation guide
[patent_app_type] => utility
[patent_app_number] => 18/430140
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 2250
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430140
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/430140 | Methods of manufacturing semiconductor chip including crack propagation guide | Jan 31, 2024 | Issued |
Array
(
[id] => 20217612
[patent_doc_number] => 12414281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Implantations for forming source/drain regions of different transistors
[patent_app_type] => utility
[patent_app_number] => 18/428994
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 1120
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428994
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428994 | Implantations for forming source/drain regions of different transistors | Jan 30, 2024 | Issued |
Array
(
[id] => 19130838
[patent_doc_number] => 20240136191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-25
[patent_title] => FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/402018
[patent_app_country] => US
[patent_app_date] => 2024-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10492
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402018
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/402018 | Fin field-effect transistor device and method of forming the same | Jan 1, 2024 | Issued |
Array
(
[id] => 20360229
[patent_doc_number] => 12476235
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-18
[patent_title] => Multi-chip packaging
[patent_app_type] => utility
[patent_app_number] => 18/397891
[patent_app_country] => US
[patent_app_date] => 2023-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 8291
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397891
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/397891 | Multi-chip packaging | Dec 26, 2023 | Issued |
Array
(
[id] => 19116449
[patent_doc_number] => 20240128199
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => SUBSTRATE PROCESSING AND PACKAGING
[patent_app_type] => utility
[patent_app_number] => 18/394178
[patent_app_country] => US
[patent_app_date] => 2023-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9809
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394178
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/394178 | SUBSTRATE PROCESSING AND PACKAGING | Dec 21, 2023 | Pending |
Array
(
[id] => 19116454
[patent_doc_number] => 20240128204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-18
[patent_title] => IC HAVING ELECTRICALLY ISOLATED WARPAGE PREVENTION STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/391463
[patent_app_country] => US
[patent_app_date] => 2023-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/391463 | IC HAVING ELECTRICALLY ISOLATED WARPAGE PREVENTION STRUCTURES | Dec 19, 2023 | Pending |
Array
(
[id] => 20080834
[patent_doc_number] => 12354911
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Cu
[patent_app_type] => utility
[patent_app_number] => 18/535536
[patent_app_country] => US
[patent_app_date] => 2023-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5498
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535536
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/535536 | Cu | Dec 10, 2023 | Issued |
Array
(
[id] => 19038304
[patent_doc_number] => 20240088119
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/515274
[patent_app_country] => US
[patent_app_date] => 2023-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6766
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515274
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/515274 | Package structure and method of forming the same | Nov 20, 2023 | Issued |
Array
(
[id] => 19980190
[patent_doc_number] => 12347677
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-01
[patent_title] => Enhanced ignition in inductively coupled plasmas for workpiece processing
[patent_app_type] => utility
[patent_app_number] => 18/503681
[patent_app_country] => US
[patent_app_date] => 2023-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7109
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503681
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/503681 | Enhanced ignition in inductively coupled plasmas for workpiece processing | Nov 6, 2023 | Issued |