Search

Susan M. Lee

Examiner (ID: 10541, Phone: (571)272-6027 , Office: P/2918 )

Most Active Art Unit
2918
Art Unit(s)
2918, 2911, 2917, 2943
Total Applications
3896
Issued Applications
3862
Pending Applications
4
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20096109 [patent_doc_number] => 20250226045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => PAGE-LEVEL AND STRIPE-BASED READ ERROR HANDLING [patent_app_type] => utility [patent_app_number] => 18/975703 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18975703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/975703
PAGE-LEVEL AND STRIPE-BASED READ ERROR HANDLING Dec 9, 2024 Pending
Array ( [id] => 20674512 [patent_doc_number] => 12615039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Sequence pattern generation device and transmission start timing control method thereof [patent_app_type] => utility [patent_app_number] => 18/975478 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3734 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18975478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/975478
Sequence pattern generation device and transmission start timing control method thereof Dec 9, 2024 Issued
Array ( [id] => 19851432 [patent_doc_number] => 20250096783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/968627 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18968627 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/968627
BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD Dec 3, 2024 Pending
Array ( [id] => 19848925 [patent_doc_number] => 20250094276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => DEVICE TRIMMING VIA DIRECT MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 18/964844 [patent_app_country] => US [patent_app_date] => 2024-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/964844
DEVICE TRIMMING VIA DIRECT MEMORY ACCESS Dec 1, 2024 Pending
Array ( [id] => 20123673 [patent_doc_number] => 20250238704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => QUANTUM OPERATION EVALUATION METHOD AND INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/961813 [patent_app_country] => US [patent_app_date] => 2024-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18961813 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/961813
QUANTUM OPERATION EVALUATION METHOD AND INFORMATION PROCESSING APPARATUS Nov 26, 2024 Pending
Array ( [id] => 20739482 [patent_doc_number] => 20260148789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => DETECTION AND COMPENSATION OF TIMING MARGIN ERRORS IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/959239 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18959239 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/959239
DETECTION AND COMPENSATION OF TIMING MARGIN ERRORS IN MEMORY Nov 24, 2024 Pending
Array ( [id] => 19804874 [patent_doc_number] => 20250070799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => DECODING DEVICE, CONTROL CIRCUIT, AND CHECK MATRIX GENERATION METHOD [patent_app_type] => utility [patent_app_number] => 18/941890 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941890 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/941890
DECODING DEVICE, CONTROL CIRCUIT, AND CHECK MATRIX GENERATION METHOD Nov 7, 2024 Pending
Array ( [id] => 19804875 [patent_doc_number] => 20250070800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => LDPC ENCODING AND DECODING METHOD AND RELATED APPARATUS [patent_app_type] => utility [patent_app_number] => 18/940997 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18940997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/940997
LDPC ENCODING AND DECODING METHOD AND RELATED APPARATUS Nov 7, 2024 Pending
Array ( [id] => 20682833 [patent_doc_number] => 20260121662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => SHAPED PARITY BIT RECOVERY VIA BIT-FLIPPING [patent_app_type] => utility [patent_app_number] => 18/932318 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932318
Shaped parity bit recovery via bit-flipping Oct 29, 2024 Issued
Array ( [id] => 19771872 [patent_doc_number] => 20250053298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => REDUCING STORAGE SYSTEM LATENCY USING INTERRUPTIBLE STORAGE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/932538 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932538 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932538
REDUCING STORAGE SYSTEM LATENCY USING INTERRUPTIBLE STORAGE OPERATIONS Oct 29, 2024 Pending
Array ( [id] => 20679610 [patent_doc_number] => 20260118424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => EFFICIENT AND HIGH COVERAGE TESTING APPROACH FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/928591 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928591 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/928591
EFFICIENT AND HIGH COVERAGE TESTING APPROACH FOR MEMORY DEVICES Oct 27, 2024 Pending
Array ( [id] => 19774178 [patent_doc_number] => 20250055604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHODS AND APPARATUS FOR HYBRID AUTOMATIC REPEAT REQUEST-ACKNOWLEDGEMENT (HARQ-ACK) CODEBOOK [patent_app_type] => utility [patent_app_number] => 18/929134 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929134
METHODS AND APPARATUS FOR HYBRID AUTOMATIC REPEAT REQUEST-ACKNOWLEDGEMENT (HARQ-ACK) CODEBOOK Oct 27, 2024 Pending
Array ( [id] => 20647340 [patent_doc_number] => 12602283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Flash memory controller and flash memory access method [patent_app_type] => utility [patent_app_number] => 18/920941 [patent_app_country] => US [patent_app_date] => 2024-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920941 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/920941
Flash memory controller and flash memory access method Oct 19, 2024 Issued
Array ( [id] => 20652943 [patent_doc_number] => 20260104962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => DECODING DATA USING A CONSTRAINED BIT-FLIPPING TECHNIQUE [patent_app_type] => utility [patent_app_number] => 18/913790 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913790
Decoding data using a constrained bit-flipping technique Oct 10, 2024 Issued
Array ( [id] => 20752353 [patent_doc_number] => 20260154583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-04 [patent_title] => Error-Correcting Codes for Fermionic Quantum Simulation [patent_app_type] => utility [patent_app_number] => 18/913257 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913257 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913257
Error-Correcting Codes for Fermionic Quantum Simulation Oct 10, 2024 Pending
Array ( [id] => 19713519 [patent_doc_number] => 20250023661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, RECEPTION METHOD, INTEGRATED CIRCUIT, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 18/904365 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/904365
TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, RECEPTION METHOD, INTEGRATED CIRCUIT, AND PROGRAM Oct 1, 2024 Pending
Array ( [id] => 20617296 [patent_doc_number] => 20260087397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => PERFORMING QUBIT MAPPING TAKING INTO CONSIDERATION CROSSTALK ERRORS IN DYNAMIC QUANTUM CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/890383 [patent_app_country] => US [patent_app_date] => 2024-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18890383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/890383
PERFORMING QUBIT MAPPING TAKING INTO CONSIDERATION CROSSTALK ERRORS IN DYNAMIC QUANTUM CIRCUITS Sep 18, 2024 Pending
Array ( [id] => 19694982 [patent_doc_number] => 20250013527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => BIT AND SIGNAL LEVEL MAPPING [patent_app_type] => utility [patent_app_number] => 18/888109 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/888109
BIT AND SIGNAL LEVEL MAPPING Sep 16, 2024 Pending
Array ( [id] => 20667999 [patent_doc_number] => 12609784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Data integrity verification for network file systems [patent_app_type] => utility [patent_app_number] => 18/886878 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/886878
Data integrity verification for network file systems Sep 15, 2024 Issued
Array ( [id] => 20580168 [patent_doc_number] => 12572419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Method and apparatus for performing data access control of memory device [patent_app_type] => utility [patent_app_number] => 18/882713 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 5657 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882713
Method and apparatus for performing data access control of memory device Sep 10, 2024 Issued
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