Search

Susannah Lee Chung

Supervisory Patent Examiner (ID: 12992, Phone: (571)272-6098 , Office: P/1768 )

Most Active Art Unit
1626
Art Unit(s)
1768, 1626, 1764
Total Applications
851
Issued Applications
565
Pending Applications
14
Abandoned Applications
277

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17508808 [patent_doc_number] => 20220101911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => NONVOLATILE MEMORY DEVICE, SYSTEM INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/465539 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465539
Nonvolatile memory device, system including the same and method for fabricating the same Sep 1, 2021 Issued
Array ( [id] => 18723436 [patent_doc_number] => 11800815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Resistive random access memory cell and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/465840 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3356 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465840
Resistive random access memory cell and method of fabricating the same Sep 1, 2021 Issued
Array ( [id] => 17295468 [patent_doc_number] => 20210391307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH THREE-DIMENSIONAL PHASE-CHANGE MEMORY [patent_app_type] => utility [patent_app_number] => 17/459339 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459339 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459339
Three-dimensional memory device with three-dimensional phase-change memory Aug 26, 2021 Issued
Array ( [id] => 18213538 [patent_doc_number] => 20230059803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => DRIVER SHARING BETWEEN BANKS OR PORTIONS OF BANKS OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/407822 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407822
Driver sharing between banks or portions of banks of memory devices Aug 19, 2021 Issued
Array ( [id] => 18876627 [patent_doc_number] => 11864473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Resistive random-access memory device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/404934 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2502 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404934 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404934
Resistive random-access memory device and method of fabricating the same Aug 16, 2021 Issued
Array ( [id] => 17862631 [patent_doc_number] => 11443792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Memory cell, memory cell arrangement, and methods thereof [patent_app_type] => utility [patent_app_number] => 17/400411 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 17779 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400411
Memory cell, memory cell arrangement, and methods thereof Aug 11, 2021 Issued
Array ( [id] => 17477535 [patent_doc_number] => 20220085039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => MEMORY STRUCTURE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/401262 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401262
Memory structure and operation method thereof Aug 11, 2021 Issued
Array ( [id] => 20332587 [patent_doc_number] => 12462871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Voltage detector for supply ramp down sequence [patent_app_type] => utility [patent_app_number] => 17/399925 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8392 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399925
Voltage detector for supply ramp down sequence Aug 10, 2021 Issued
Array ( [id] => 18181221 [patent_doc_number] => 20230041950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH SEPARATED CONTACT REGIONS AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/397846 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397846
Three-dimensional memory device with separated contact regions and methods for forming the same Aug 8, 2021 Issued
Array ( [id] => 18892761 [patent_doc_number] => 11871554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Semiconductor structure, and manufacturing method and control method thereof [patent_app_type] => utility [patent_app_number] => 17/391195 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 48 [patent_no_of_words] => 6880 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391195
Semiconductor structure, and manufacturing method and control method thereof Aug 1, 2021 Issued
Array ( [id] => 17738243 [patent_doc_number] => 20220223705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => STEEP-SLOPE FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/437368 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17437368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/437368
Steep-slope field-effect transistor and fabrication method thereof Jul 28, 2021 Issued
Array ( [id] => 18671873 [patent_doc_number] => 11778806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory device having 2-transistor vertical memory cell and separate read and write gates [patent_app_type] => utility [patent_app_number] => 17/388678 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 14519 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388678 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388678
Memory device having 2-transistor vertical memory cell and separate read and write gates Jul 28, 2021 Issued
Array ( [id] => 18008174 [patent_doc_number] => 20220366941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/387924 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387924
Memory device and method of forming the same Jul 27, 2021 Issued
Array ( [id] => 17787606 [patent_doc_number] => 11410740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Multi-fuse memory cell circuit and method [patent_app_type] => utility [patent_app_number] => 17/378923 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17378923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/378923
Multi-fuse memory cell circuit and method Jul 18, 2021 Issued
Array ( [id] => 17941494 [patent_doc_number] => 11475953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Semiconductor layout pattern and forming method thereof [patent_app_type] => utility [patent_app_number] => 17/377396 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2889 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377396
Semiconductor layout pattern and forming method thereof Jul 15, 2021 Issued
Array ( [id] => 17203622 [patent_doc_number] => 20210343717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/374186 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/374186
Semiconductor storage device Jul 12, 2021 Issued
Array ( [id] => 17389487 [patent_doc_number] => 20220037339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => INTEGRATED CIRCUIT INCLUDING MEMORY CELL AND METHOD OF DESIGNING THE SAME [patent_app_type] => utility [patent_app_number] => 17/371522 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371522
Integrated circuit including memory cell and method of designing the same Jul 8, 2021 Issued
Array ( [id] => 18876630 [patent_doc_number] => 11864476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Electronic device [patent_app_type] => utility [patent_app_number] => 17/369725 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11786 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369725
Electronic device Jul 6, 2021 Issued
Array ( [id] => 19294333 [patent_doc_number] => 12033694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Semiconductor device and electronic device [patent_app_type] => utility [patent_app_number] => 18/007766 [patent_app_country] => US [patent_app_date] => 2021-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 83 [patent_no_of_words] => 80558 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18007766 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/007766
Semiconductor device and electronic device Jul 4, 2021 Issued
Array ( [id] => 18112640 [patent_doc_number] => 20230005520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SEMICONDUCTOR DEVICE HAVING A TEST CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/364829 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364829
Semiconductor device having a test circuit Jun 29, 2021 Issued
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