
Susanne Christine Tinker
Examiner (ID: 15244)
| Most Active Art Unit | 3404 |
| Art Unit(s) | 3744, 3404 |
| Total Applications | 374 |
| Issued Applications | 327 |
| Pending Applications | 32 |
| Abandoned Applications | 15 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4639405
[patent_doc_number] => 08017432
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-13
[patent_title] => 'Deposition of amorphous phase change material'
[patent_app_type] => utility
[patent_app_number] => 12/684185
[patent_app_country] => US
[patent_app_date] => 2010-01-08
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/017/08017432.pdf
[firstpage_image] =>[orig_patent_app_number] => 12684185
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/684185 | Deposition of amorphous phase change material | Jan 7, 2010 | Issued |
Array
(
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[patent_doc_number] => 20100184269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-22
[patent_title] => 'METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/684269
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/684269 | Method for manufacturing SOI substrate and semiconductor device | Jan 7, 2010 | Issued |
Array
(
[id] => 7977421
[patent_doc_number] => 08071457
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Low capacitance precision resistor'
[patent_app_type] => utility
[patent_app_number] => 12/683770
[patent_app_country] => US
[patent_app_date] => 2010-01-07
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[pdf_file] => patents/08/071/08071457.pdf
[firstpage_image] =>[orig_patent_app_number] => 12683770
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/683770 | Low capacitance precision resistor | Jan 6, 2010 | Issued |
Array
(
[id] => 6099048
[patent_doc_number] => 20110163455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-07-07
[patent_title] => 'Tunnel Junction Via'
[patent_app_type] => utility
[patent_app_number] => 12/683080
[patent_app_country] => US
[patent_app_date] => 2010-01-06
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12683080
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/683080 | Tunnel junction via | Jan 5, 2010 | Issued |
Array
(
[id] => 6633935
[patent_doc_number] => 20100173497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-08
[patent_title] => 'Method of fabricating semiconductor integrated circuit device'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2010-01-06
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/655837 | Method of fabricating semiconductor integrated circuit device | Jan 5, 2010 | Abandoned |
Array
(
[id] => 6230510
[patent_doc_number] => 20100184284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-22
[patent_title] => 'Method of Manufacturing Semiconductor Memory Device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/648842 | Method of Manufacturing Semiconductor Memory Device | Dec 28, 2009 | Abandoned |
Array
(
[id] => 6293232
[patent_doc_number] => 20100159696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'MICROLENS MASK OF IMAGE SENSOR AND METHOD FOR FORMING MICROLENS USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/644702
[patent_app_country] => US
[patent_app_date] => 2009-12-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0159/20100159696.pdf
[firstpage_image] =>[orig_patent_app_number] => 12644702
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/644702 | MICROLENS MASK OF IMAGE SENSOR AND METHOD FOR FORMING MICROLENS USING THE SAME | Dec 21, 2009 | Abandoned |
Array
(
[id] => 7742014
[patent_doc_number] => 08106518
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-31
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/640766
[patent_app_country] => US
[patent_app_date] => 2009-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
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[pdf_file] => patents/08/106/08106518.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/640766 | Semiconductor device and method of manufacturing the same | Dec 16, 2009 | Issued |
Array
(
[id] => 6419020
[patent_doc_number] => 20100167475
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-01
[patent_title] => 'SEMICONDUCTOR DEVICE AND PRODUCING METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/639561 | Semiconductor device and producing method thereof | Dec 15, 2009 | Issued |
Array
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[id] => 6438946
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[patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE'
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[patent_app_number] => 12/627572
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/627572 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | Nov 29, 2009 | Abandoned |
Array
(
[id] => 8968499
[patent_doc_number] => 08507310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-13
[patent_title] => 'Method for manufacturing thin-film photoelectric conversion device'
[patent_app_type] => utility
[patent_app_number] => 13/129612
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/129612 | Method for manufacturing thin-film photoelectric conversion device | Nov 19, 2009 | Issued |
Array
(
[id] => 6448534
[patent_doc_number] => 20100105170
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[patent_title] => 'Method for manufacturing a semiconductor device having a heat spreader'
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Array
(
[id] => 6255238
[patent_doc_number] => 20100029081
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[patent_title] => 'SINGLE SPACER PROCESS FOR MULTIPLYING PITCH BY A FACTOR GREATER THAN TWO AND RELATED INTERMEDIATE IC STRUCTURES'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/577342 | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures | Oct 11, 2009 | Issued |
Array
(
[id] => 6500621
[patent_doc_number] => 20100012858
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[patent_title] => 'METHODS FOR FORMING DENSE DIELECTRIC LAYER OVER POROUS DIELECTRICS'
[patent_app_type] => utility
[patent_app_number] => 12/569077
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Array
(
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Array
(
[id] => 5461646
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[patent_title] => 'Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, and Related Device'
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Array
(
[id] => 5971015
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[patent_title] => 'PHOTOVOLTAIC CELL MANUFACTURING METHOD'
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/510549 | METHOD FOR PRODUCING BONDED WAFER | Jul 27, 2009 | Abandoned |