Search

Susy N. Tsang Foster

Examiner (ID: 3540)

Most Active Art Unit
1745
Art Unit(s)
1745, 1753, 1795
Total Applications
451
Issued Applications
316
Pending Applications
57
Abandoned Applications
78

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12615711 [patent_doc_number] => 20180097067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/683029 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683029
Semiconductor device and manufacturing method therefor Aug 21, 2017 Issued
Array ( [id] => 12223611 [patent_doc_number] => 20180061971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'Transistor Device with High Current Robustness' [patent_app_type] => utility [patent_app_number] => 15/682807 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7277 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682807
Transistor device with high current robustness Aug 21, 2017 Issued
Array ( [id] => 13543603 [patent_doc_number] => 20180323348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => ILLUMINATION DEVICE FOR DESORBING MOLECULES FROM INNER WALLS OF A PROCESSING CHAMBER [patent_app_type] => utility [patent_app_number] => 15/682921 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682921
Illumination device for desorbing molecules from inner walls of a processing chamber Aug 21, 2017 Issued
Array ( [id] => 12223426 [patent_doc_number] => 20180061786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEMICONDUCTOR PACKAGE INTEGRATED WITH MEMORY DIE' [patent_app_type] => utility [patent_app_number] => 15/682908 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4838 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682908 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682908
Semiconductor package integrated with memory die Aug 21, 2017 Issued
Array ( [id] => 15376151 [patent_doc_number] => 10529804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method [patent_app_type] => utility [patent_app_number] => 15/682128 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6111 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682128 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682128
Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method Aug 20, 2017 Issued
Array ( [id] => 14738503 [patent_doc_number] => 10388661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/682003 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 38 [patent_no_of_words] => 8494 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682003
Semiconductor device and method of manufacturing the same Aug 20, 2017 Issued
Array ( [id] => 13936075 [patent_doc_number] => 20190051553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => Methods of Transferring a Graphene Monolayer via a Stacked Structure and Devices Fabricated Thereby [patent_app_type] => utility [patent_app_number] => 15/674852 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674852 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674852
Methods of Transferring a Graphene Monolayer via a Stacked Structure and Devices Fabricated Thereby Aug 10, 2017 Abandoned
Array ( [id] => 12187150 [patent_doc_number] => 20180046086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'METHODS OF REDUCING METAL RESIDUE IN EDGE BEAD REGION FROM METAL-CONTAINING RESISTS' [patent_app_type] => utility [patent_app_number] => 15/674934 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9419 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674934 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674934
Methods of reducing metal residue in edge bead region from metal-containing resists Aug 10, 2017 Issued
Array ( [id] => 17825790 [patent_doc_number] => 11430744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Die-attach method to compensate for thermal expansion [patent_app_type] => utility [patent_app_number] => 15/673734 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15673734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/673734
Die-attach method to compensate for thermal expansion Aug 9, 2017 Issued
Array ( [id] => 13936099 [patent_doc_number] => 20190051565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => CMOS DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/673519 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15673519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/673519
CMOS DEVICES AND MANUFACTURING METHOD THEREOF Aug 9, 2017 Abandoned
Array ( [id] => 12208435 [patent_doc_number] => 20180053660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'METHOD FOR PREVENTING LINE BENDING DURING METAL FILL PROCESS' [patent_app_type] => utility [patent_app_number] => 15/673320 [patent_app_country] => US [patent_app_date] => 2017-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 20637 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15673320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/673320
Method for preventing line bending during metal fill process Aug 8, 2017 Issued
Array ( [id] => 12054570 [patent_doc_number] => 20170330913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'SUBSTRATE WITH CONDUCTIVE FILM' [patent_app_type] => utility [patent_app_number] => 15/666038 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8217 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15666038 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/666038
Substrate with conductive film Jul 31, 2017 Issued
Array ( [id] => 13293637 [patent_doc_number] => 10158019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Source/drain junction formation [patent_app_type] => utility [patent_app_number] => 15/664436 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15664436 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/664436
Source/drain junction formation Jul 30, 2017 Issued
Array ( [id] => 12026873 [patent_doc_number] => 20170316972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'GLOBAL DIELECTRIC AND BARRIER LAYER' [patent_app_type] => utility [patent_app_number] => 15/651939 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651939
Global dielectric and barrier layer Jul 16, 2017 Issued
Array ( [id] => 12026875 [patent_doc_number] => 20170316973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/651476 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651476
Method for manufacturing a semiconductor device Jul 16, 2017 Issued
Array ( [id] => 11983526 [patent_doc_number] => 20170287680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'Ceramic Layer for Electrostatic Chuck Including Embedded Faraday Cage for RF Delivery and Associated Methods' [patent_app_type] => utility [patent_app_number] => 15/628528 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628528
Ceramic layer for electrostatic chuck including embedded faraday cage for RF delivery and associated methods Jun 19, 2017 Issued
Array ( [id] => 14525727 [patent_doc_number] => 10340134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Semiconductor device manufacturing method, substrate processing apparatus, and recording medium [patent_app_type] => utility [patent_app_number] => 15/627828 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 17730 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627828
Semiconductor device manufacturing method, substrate processing apparatus, and recording medium Jun 19, 2017 Issued
Array ( [id] => 18343511 [patent_doc_number] => 11640995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Ferroelectric field effect transistors (FeFETs) having band-engineered interface layer [patent_app_type] => utility [patent_app_number] => 16/616373 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 13072 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16616373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/616373
Ferroelectric field effect transistors (FeFETs) having band-engineered interface layer Jun 19, 2017 Issued
Array ( [id] => 14382389 [patent_doc_number] => 20190165107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => APPARATUSES WITH ATOMICALLY-THIN OHMIC EDGE CONTACTS BETWEEN TWO-DIMENSIONAL MATERIALS, METHODS OF MAKING SAME, AND DEVICES COMPRISING SAME [patent_app_type] => utility [patent_app_number] => 16/309637 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16309637 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/309637
Apparatuses with atomically-thin ohmic edge contacts between two-dimensional materials, methods of making same, and devices comprising same Jun 12, 2017 Issued
Array ( [id] => 11969470 [patent_doc_number] => 20170273624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'ELECTRONIC SKIN AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/618976 [patent_app_country] => US [patent_app_date] => 2017-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3643 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15618976 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/618976
Electronic skin and manufacturing method therefor Jun 8, 2017 Issued
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