Search

Tae W. Kim

Examiner (ID: 15101, Phone: (571)272-5971 , Office: P/2887 )

Most Active Art Unit
2887
Art Unit(s)
2876, 2887
Total Applications
494
Issued Applications
273
Pending Applications
55
Abandoned Applications
173

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12739384 [patent_doc_number] => 20180138295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => METHOD OF MANUFACTURING A THIN FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/121928 [patent_app_country] => US [patent_app_date] => 2016-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15121928 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/121928
Method of manufacturing a thin film transistor Apr 7, 2016 Issued
Array ( [id] => 11718112 [patent_doc_number] => 20170186611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'POLYCRYSTALLINE SILICON THIN FILM AND METHOD THEREOF, OPTICAL FILM, AND THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/305588 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5915 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15305588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/305588
POLYCRYSTALLINE SILICON THIN FILM AND METHOD THEREOF, OPTICAL FILM, AND THIN FILM TRANSISTOR Apr 5, 2016 Abandoned
Array ( [id] => 15641199 [patent_doc_number] => 10593604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-17 [patent_title] => Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells [patent_app_type] => utility [patent_app_number] => 15/090267 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2552 [patent_figures_cnt] => 7276 [patent_no_of_words] => 116207 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090267 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090267
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells Apr 3, 2016 Issued
Array ( [id] => 13755287 [patent_doc_number] => 10170598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/057457 [patent_app_country] => US [patent_app_date] => 2016-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 47 [patent_no_of_words] => 13057 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057457 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057457
Semiconductor device and method for manufacturing the same Feb 29, 2016 Issued
Array ( [id] => 10826175 [patent_doc_number] => 20160172343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'Light-Emitting Diode Device' [patent_app_type] => utility [patent_app_number] => 15/050271 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3278 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/050271
Light-Emitting Diode Device Feb 21, 2016 Abandoned
Array ( [id] => 11007328 [patent_doc_number] => 20160204280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'LATERAL CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR WORDLINE' [patent_app_type] => utility [patent_app_number] => 15/048886 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/048886
Lateral charge storage region formation for semiconductor wordline Feb 18, 2016 Issued
Array ( [id] => 12214875 [patent_doc_number] => 09911690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Interconnect structures with fully aligned vias' [patent_app_type] => utility [patent_app_number] => 15/044154 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4518 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15044154 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/044154
Interconnect structures with fully aligned vias Feb 15, 2016 Issued
Array ( [id] => 14151843 [patent_doc_number] => 10256311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Fin field effect transistor (FinFET) [patent_app_type] => utility [patent_app_number] => 15/016473 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016473 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016473
Fin field effect transistor (FinFET) Feb 4, 2016 Issued
Array ( [id] => 10809734 [patent_doc_number] => 20160155893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'ENGINEERED SUBSTRATES FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 15/016943 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6567 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016943
Engineered substrates for semiconductor devices and associated systems and methods Feb 4, 2016 Issued
Array ( [id] => 12801688 [patent_doc_number] => 20180159066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => ARRAY SUBSTRATE, DISPLAY PANEL, DISPLAY DEVICE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 15/525500 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15525500 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/525500
Array substrate, display panel, display device, method for manufacturing array substrate and method for manufacturing display panel Dec 16, 2015 Issued
Array ( [id] => 10826034 [patent_doc_number] => 20160172202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'INTEGRATED CIRCUITS WITH BACKSIDE METALIZATION AND PRODUCTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/970637 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4375 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970637 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/970637
Integrated circuits with backside metalization and production method thereof Dec 15, 2015 Issued
Array ( [id] => 11459933 [patent_doc_number] => 20170053839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'SEMICONDUCTOR STRUCTURES HAVING INCREASED CHANNEL STRAIN USING FIN RELEASE IN GATE REGIONS' [patent_app_type] => utility [patent_app_number] => 14/953519 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2858 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953519 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/953519
Semiconductor structures having increased channel strain using fin release in gate regions Nov 29, 2015 Issued
Array ( [id] => 13271463 [patent_doc_number] => 10147818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Enhanced method of stressing a transistor channel zone [patent_app_type] => utility [patent_app_number] => 14/950416 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 4216 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950416 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950416
Enhanced method of stressing a transistor channel zone Nov 23, 2015 Issued
Array ( [id] => 11653054 [patent_doc_number] => 20170148955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'Method of wafer level packaging of a module' [patent_app_type] => utility [patent_app_number] => 14/948366 [patent_app_country] => US [patent_app_date] => 2015-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4524 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948366
Method of wafer level packaging of a module Nov 21, 2015 Abandoned
Array ( [id] => 11652773 [patent_doc_number] => 20170148674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'THROUGH SUBSTRATE VIA LINER DENSIFICATION' [patent_app_type] => utility [patent_app_number] => 14/948074 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6100 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948074 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948074
Through substrate via liner densification Nov 19, 2015 Issued
Array ( [id] => 13019259 [patent_doc_number] => 10032749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Three-dimensional chip-to-wafer integration [patent_app_type] => utility [patent_app_number] => 14/942708 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4190 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942708 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942708
Three-dimensional chip-to-wafer integration Nov 15, 2015 Issued
Array ( [id] => 11551625 [patent_doc_number] => 09620483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Semiconductor integrated circuit including power TSVS' [patent_app_type] => utility [patent_app_number] => 14/928586 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2742 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928586 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/928586
Semiconductor integrated circuit including power TSVS Oct 29, 2015 Issued
Array ( [id] => 11728491 [patent_doc_number] => 20170189934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'OLED Display Panel And Method For Preparing The Same' [patent_app_type] => utility [patent_app_number] => 14/892326 [patent_app_country] => US [patent_app_date] => 2015-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2065 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14892326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/892326
OLED Display Panel And Method For Preparing The Same Oct 25, 2015 Abandoned
Array ( [id] => 10697013 [patent_doc_number] => 20160043160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/920642 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15738 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920642 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920642
Organic light emitting diode display device and method of fabricating the same Oct 21, 2015 Issued
Array ( [id] => 10802829 [patent_doc_number] => 20160148986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'TRANSISTOR, ORGANIC LIGHT EMITTING DISPLAY HAVING THE SAME, AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY' [patent_app_type] => utility [patent_app_number] => 14/919666 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7050 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919666 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/919666
Transistor, organic light emitting display having the same, and method of manufacturing organic light emitting display Oct 20, 2015 Issued
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