Search

Taeho Jo

Examiner (ID: 12093, Phone: (571)272-3325 , Office: P/2884 )

Most Active Art Unit
2884
Art Unit(s)
2884
Total Applications
584
Issued Applications
481
Pending Applications
1
Abandoned Applications
101

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2822761 [patent_doc_number] => 05168073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-01 [patent_title] => 'Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate' [patent_app_type] => 1 [patent_app_number] => 7/786143 [patent_app_country] => US [patent_app_date] => 1991-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5107 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/168/05168073.pdf [firstpage_image] =>[orig_patent_app_number] => 786143 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/786143
Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate Oct 30, 1991 Issued
07/783341 METHOD FOR MANUFACTURING ULSI SEMICONDUCTOR MEMORY DEVICE Oct 27, 1991 Abandoned
Array ( [id] => 2850747 [patent_doc_number] => 05126284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Method of inductively contacting semiconductor regions' [patent_app_type] => 1 [patent_app_number] => 7/782825 [patent_app_country] => US [patent_app_date] => 1991-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6215 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126284.pdf [firstpage_image] =>[orig_patent_app_number] => 782825 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/782825
Method of inductively contacting semiconductor regions Oct 24, 1991 Issued
Array ( [id] => 2829508 [patent_doc_number] => 05175120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors' [patent_app_type] => 1 [patent_app_number] => 7/776073 [patent_app_country] => US [patent_app_date] => 1991-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 3834 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175120.pdf [firstpage_image] =>[orig_patent_app_number] => 776073 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/776073
Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors Oct 10, 1991 Issued
Array ( [id] => 2822890 [patent_doc_number] => 05169790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Method of making thyristor having low reflection light-triggering structure' [patent_app_type] => 1 [patent_app_number] => 7/774605 [patent_app_country] => US [patent_app_date] => 1991-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1531 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169790.pdf [firstpage_image] =>[orig_patent_app_number] => 774605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/774605
Method of making thyristor having low reflection light-triggering structure Oct 9, 1991 Issued
Array ( [id] => 2882015 [patent_doc_number] => 05108943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Mushroom double stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 7/763845 [patent_app_country] => US [patent_app_date] => 1991-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 2571 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/108/05108943.pdf [firstpage_image] =>[orig_patent_app_number] => 763845 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/763845
Mushroom double stacked capacitor Sep 22, 1991 Issued
Array ( [id] => 2982296 [patent_doc_number] => 05250456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-05 [patent_title] => 'Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby' [patent_app_type] => 1 [patent_app_number] => 7/759465 [patent_app_country] => US [patent_app_date] => 1991-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4893 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/250/05250456.pdf [firstpage_image] =>[orig_patent_app_number] => 759465 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/759465
Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby Sep 12, 1991 Issued
Array ( [id] => 2966796 [patent_doc_number] => 05202278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Method of forming a capacitor in semiconductor wafer processing' [patent_app_type] => 1 [patent_app_number] => 7/757197 [patent_app_country] => US [patent_app_date] => 1991-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2346 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202278.pdf [firstpage_image] =>[orig_patent_app_number] => 757197 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/757197
Method of forming a capacitor in semiconductor wafer processing Sep 9, 1991 Issued
Array ( [id] => 2893203 [patent_doc_number] => 05240871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Corrugated storage contact capacitor and method for forming a corrugated storage contact capacitor' [patent_app_type] => 1 [patent_app_number] => 7/755985 [patent_app_country] => US [patent_app_date] => 1991-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3048 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/240/05240871.pdf [firstpage_image] =>[orig_patent_app_number] => 755985 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/755985
Corrugated storage contact capacitor and method for forming a corrugated storage contact capacitor Sep 5, 1991 Issued
Array ( [id] => 2915348 [patent_doc_number] => 05179033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Method for manufacturing TFT SRAM' [patent_app_type] => 1 [patent_app_number] => 7/754615 [patent_app_country] => US [patent_app_date] => 1991-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 2662 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179033.pdf [firstpage_image] =>[orig_patent_app_number] => 754615 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/754615
Method for manufacturing TFT SRAM Sep 3, 1991 Issued
07/755259 ANTI-FUSE STRUCTURES AND METHODS FOR MAKING SAME Sep 3, 1991 Abandoned
Array ( [id] => 2909971 [patent_doc_number] => 05236856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Method for minimizing diffusion of conductivity enhancing impurities from one region of polysilicon layer to another region and a semiconductor device produced according to the method' [patent_app_type] => 1 [patent_app_number] => 7/753355 [patent_app_country] => US [patent_app_date] => 1991-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2608 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/236/05236856.pdf [firstpage_image] =>[orig_patent_app_number] => 753355 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/753355
Method for minimizing diffusion of conductivity enhancing impurities from one region of polysilicon layer to another region and a semiconductor device produced according to the method Aug 29, 1991 Issued
07/747663 SELF-ALIGNED STACKED GATE EPROM CELL USING TANTALUM OXIDE CONTROL GATE DIELECTRIC Aug 19, 1991 Abandoned
Array ( [id] => 2822983 [patent_doc_number] => 05169795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Method of manufacturing step cut type insulated gate SIT having low-resistance electrode' [patent_app_type] => 1 [patent_app_number] => 7/747699 [patent_app_country] => US [patent_app_date] => 1991-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 5368 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169795.pdf [firstpage_image] =>[orig_patent_app_number] => 747699 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/747699
Method of manufacturing step cut type insulated gate SIT having low-resistance electrode Aug 19, 1991 Issued
Array ( [id] => 2890213 [patent_doc_number] => 05270228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method of fabricating gate electrode in recess' [patent_app_type] => 1 [patent_app_number] => 7/745333 [patent_app_country] => US [patent_app_date] => 1991-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 5029 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270228.pdf [firstpage_image] =>[orig_patent_app_number] => 745333 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/745333
Method of fabricating gate electrode in recess Aug 14, 1991 Issued
Array ( [id] => 2978775 [patent_doc_number] => 05204284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Method of making a high band-gap opto-electronic device' [patent_app_type] => 1 [patent_app_number] => 7/744569 [patent_app_country] => US [patent_app_date] => 1991-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6260 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204284.pdf [firstpage_image] =>[orig_patent_app_number] => 744569 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/744569
Method of making a high band-gap opto-electronic device Aug 12, 1991 Issued
07/742045 METHOD FOR MANUFACTURING A VLSI SEMICONDUCTOR DEVICE Aug 7, 1991 Abandoned
Array ( [id] => 2930096 [patent_doc_number] => 05219776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/737029 [patent_app_country] => US [patent_app_date] => 1991-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2579 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/219/05219776.pdf [firstpage_image] =>[orig_patent_app_number] => 737029 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/737029
Method of manufacturing semiconductor device Jul 28, 1991 Issued
Array ( [id] => 2920819 [patent_doc_number] => 05200350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Floating-gate memory array with silicided buried bitlines' [patent_app_type] => 1 [patent_app_number] => 7/736337 [patent_app_country] => US [patent_app_date] => 1991-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/200/05200350.pdf [firstpage_image] =>[orig_patent_app_number] => 736337 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/736337
Floating-gate memory array with silicided buried bitlines Jul 25, 1991 Issued
Array ( [id] => 2788335 [patent_doc_number] => 05135877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Method of making a light-emitting diode with anti-reflection layer optimization' [patent_app_type] => 1 [patent_app_number] => 7/732899 [patent_app_country] => US [patent_app_date] => 1991-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3368 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/135/05135877.pdf [firstpage_image] =>[orig_patent_app_number] => 732899 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/732899
Method of making a light-emitting diode with anti-reflection layer optimization Jul 18, 1991 Issued
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