Search

Tamara Y. Washington

Examiner (ID: 11545, Phone: (571)270-3887 , Office: P/2872 )

Most Active Art Unit
2872
Art Unit(s)
2872
Total Applications
771
Issued Applications
610
Pending Applications
77
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19023192 [patent_doc_number] => 20240079363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 18/237489 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237489
INTEGRATED CIRCUIT PACKAGE Aug 23, 2023 Pending
Array ( [id] => 19178110 [patent_doc_number] => 20240164084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/236435 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236435 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/236435
SEMICONDUCTOR DEVICE Aug 21, 2023 Pending
Array ( [id] => 19788508 [patent_doc_number] => 20250062187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => Direct Vapor Chamber for Heat Dissipation in Electronic Devices [patent_app_type] => utility [patent_app_number] => 18/235851 [patent_app_country] => US [patent_app_date] => 2023-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235851
Direct Vapor Chamber for Heat Dissipation in Electronic Devices Aug 19, 2023 Pending
Array ( [id] => 19346885 [patent_doc_number] => 20240255848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR PHOTORESIST COMPOSITION AND METHOD OF FORMING PATTERNS USING THE COMPOSITION [patent_app_type] => utility [patent_app_number] => 18/449156 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449156 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/449156
SEMICONDUCTOR PHOTORESIST COMPOSITION AND METHOD OF FORMING PATTERNS USING THE COMPOSITION Aug 13, 2023 Pending
Array ( [id] => 19040379 [patent_doc_number] => 20240090194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => CAPACITOR, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/232413 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232413 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232413
Capacitor, semiconductor device, and manufacturing method of semiconductor device Aug 9, 2023 Issued
Array ( [id] => 18812860 [patent_doc_number] => 20230387197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION [patent_app_type] => utility [patent_app_number] => 18/232545 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232545
NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION Aug 9, 2023 Pending
Array ( [id] => 19038336 [patent_doc_number] => 20240088151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => S-Contact for SOI [patent_app_type] => utility [patent_app_number] => 18/447200 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447200 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447200
S-contact for SOI Aug 8, 2023 Issued
Array ( [id] => 19244574 [patent_doc_number] => 12015029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Method to embed planar FETs with finFETs [patent_app_type] => utility [patent_app_number] => 18/365424 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 96 [patent_no_of_words] => 16015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365424
Method to embed planar FETs with finFETs Aug 3, 2023 Issued
Array ( [id] => 18959080 [patent_doc_number] => 20240047407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 18/228898 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228898
INTEGRATED CIRCUIT PACKAGE Jul 31, 2023 Pending
Array ( [id] => 19261069 [patent_doc_number] => 12021136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Gate isolation feature and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/361556 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361556 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361556
Gate isolation feature and manufacturing method thereof Jul 27, 2023 Issued
Array ( [id] => 19751637 [patent_doc_number] => 20250040202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => METHODS AND DEVICES FOR VERTICAL CONNECTION WITH INTERNAL EPITAXIAL STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/227059 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227059
METHODS AND DEVICES FOR VERTICAL CONNECTION WITH INTERNAL EPITAXIAL STRUCTURE Jul 26, 2023 Pending
Array ( [id] => 19588679 [patent_doc_number] => 20240386236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => FLOW FIELD IDENTIFICATION METHOD OF ARTIFICIAL INTELLIGENCE FISH SIMULATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/226783 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226783
FLOW FIELD IDENTIFICATION METHOD OF ARTIFICIAL INTELLIGENCE FISH SIMULATION SYSTEM Jul 26, 2023 Abandoned
Array ( [id] => 18774445 [patent_doc_number] => 20230369276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/226961 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226961
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Jul 26, 2023 Pending
Array ( [id] => 19749490 [patent_doc_number] => 20250038055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Submounts with Stud Protrusions for Semiconductor Packages [patent_app_type] => utility [patent_app_number] => 18/358616 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358616
Submounts with Stud Protrusions for Semiconductor Packages Jul 24, 2023 Pending
Array ( [id] => 19260876 [patent_doc_number] => 12020941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Dipole-engineered high-k gate dielectric and method forming same [patent_app_type] => utility [patent_app_number] => 18/356860 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 8469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356860
Dipole-engineered high-k gate dielectric and method forming same Jul 20, 2023 Issued
Array ( [id] => 19619406 [patent_doc_number] => 20240405086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/224582 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224582 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224582
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Jul 20, 2023 Pending
Array ( [id] => 19671036 [patent_doc_number] => 12183808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers [patent_app_type] => utility [patent_app_number] => 18/355253 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 7040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355253 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355253
Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers Jul 18, 2023 Issued
Array ( [id] => 19305679 [patent_doc_number] => 20240234259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => Lead Frame, Packaging Structure and Packaging Method [patent_app_type] => utility [patent_app_number] => 18/220980 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220980
Lead Frame, Packaging Structure and Packaging Method Jul 11, 2023 Issued
Array ( [id] => 19176141 [patent_doc_number] => 20240162115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/218322 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218322
SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME Jul 4, 2023 Pending
Array ( [id] => 19688142 [patent_doc_number] => 20250006687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => HEAT DISSIPATION IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/345248 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345248
HEAT DISSIPATION IN SEMICONDUCTOR DEVICES Jun 29, 2023 Pending
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