Search

Tammara R. Peyton

Examiner (ID: 5819, Phone: (571)272-4157 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2182, 2782
Total Applications
1681
Issued Applications
1471
Pending Applications
81
Abandoned Applications
147

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17069201 [patent_doc_number] => 20210271417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MEMORY DEVICE AND SCHEDULING METHOD FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/985240 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16985240 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/985240
Memory device for scheduling maximum number of memory macros write operations at re-arranged time intervals Aug 4, 2020 Issued
Array ( [id] => 18030797 [patent_doc_number] => 11513986 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-29 [patent_title] => DMA engine that generates an address-less memory descriptor that does not include a memory address for communicating with integrated circuit device [patent_app_type] => utility [patent_app_number] => 16/983131 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11553 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983131
DMA engine that generates an address-less memory descriptor that does not include a memory address for communicating with integrated circuit device Aug 2, 2020 Issued
Array ( [id] => 17515542 [patent_doc_number] => 11294692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Basic input output system (BIOS)--identified memory size and node address range mirroring system [patent_app_type] => utility [patent_app_number] => 16/940098 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940098
Basic input output system (BIOS)--identified memory size and node address range mirroring system Jul 26, 2020 Issued
Array ( [id] => 17372117 [patent_doc_number] => 20220027169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => Application and Related Object Schematic Viewer [patent_app_type] => utility [patent_app_number] => 16/934356 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934356
Application and related object schematic viewer for software application change tracking and management Jul 20, 2020 Issued
Array ( [id] => 16559190 [patent_doc_number] => 20210004339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Digital Interface Circuit for Analog-to-Digital Converter [patent_app_type] => utility [patent_app_number] => 16/933752 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933752
Digital interface circuit for sequencing analog-to-digital converter Jul 19, 2020 Issued
Array ( [id] => 16615912 [patent_doc_number] => 20210034565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => RECALIBRATION OF PHY CIRCUITRY FOR THE PCI EXPRESS (PIPE) INTERFACE BASED ON USING A MESSAGE BUS INTERFACE [patent_app_type] => utility [patent_app_number] => 16/926524 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926524
Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface Jul 9, 2020 Issued
Array ( [id] => 17252993 [patent_doc_number] => 11188482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Apparatus and method of zero-copy application co-processor with storage class memory [patent_app_type] => utility [patent_app_number] => 16/917392 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5449 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917392
Apparatus and method of zero-copy application co-processor with storage class memory Jun 29, 2020 Issued
Array ( [id] => 17352135 [patent_doc_number] => 11226772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-18 [patent_title] => Peak power reduction management in non-volatile storage by delaying start times operations [patent_app_type] => utility [patent_app_number] => 16/912381 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 17458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912381
Peak power reduction management in non-volatile storage by delaying start times operations Jun 24, 2020 Issued
Array ( [id] => 16844828 [patent_doc_number] => 11016917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Data storage system and method for multiple communication protocols and direct memory access [patent_app_type] => utility [patent_app_number] => 16/911312 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911312 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911312
Data storage system and method for multiple communication protocols and direct memory access Jun 23, 2020 Issued
Array ( [id] => 16615830 [patent_doc_number] => 20210034483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => COMPUTER DUPLICATION AND CONFIGURATION MANAGEMENT SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 16/900914 [patent_app_country] => US [patent_app_date] => 2020-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900914 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900914
Computer duplication and configuration management systems and methods Jun 12, 2020 Issued
Array ( [id] => 17492277 [patent_doc_number] => 11281580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Edge device triggering a write-ahead logging (WAL) log when abnormal condition occurs [patent_app_type] => utility [patent_app_number] => 16/896699 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5994 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896699
Edge device triggering a write-ahead logging (WAL) log when abnormal condition occurs Jun 8, 2020 Issued
Array ( [id] => 16730074 [patent_doc_number] => 20210097221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => OPTIMIZATION METHOD FOR GRAPH PROCESSING BASED ON HETEROGENEOUS FPGA DATA STREAMS [patent_app_type] => utility [patent_app_number] => 16/895545 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 559 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895545 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895545
Optimization method for graph processing based on heterogeneous FPGA data streams Jun 7, 2020 Issued
Array ( [id] => 17245524 [patent_doc_number] => 20210365268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => OPERATIONAL CODE STORAGE FOR AN ON-DIE MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 16/878226 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878226 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878226
Operational code storage for an on-die microprocessor May 18, 2020 Issued
Array ( [id] => 17454656 [patent_doc_number] => 11269515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Secure authentication for debugging data transferred over a system management bus [patent_app_type] => utility [patent_app_number] => 15/929659 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929659
Secure authentication for debugging data transferred over a system management bus May 13, 2020 Issued
Array ( [id] => 17230587 [patent_doc_number] => 20210357144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => SECURELY ARMING A MEMORY DEVICE FOR SELF-DESTRUCTION [patent_app_type] => utility [patent_app_number] => 15/930963 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930963
Securely arming a memory device for self-destruction by implementing a self-destruction countdown timer using a battery backed real-time clock May 12, 2020 Issued
Array ( [id] => 17230590 [patent_doc_number] => 20210357147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => METHOD AND SYSTEM FOR FACILITATING MEMORY MEDIA AS A FILE STORAGE DEVICE BASED ON REAL-TIME HASHING [patent_app_type] => utility [patent_app_number] => 15/931067 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931067
System method for facilitating memory media as file storage device based on real-time hashing by performing integrity check with a cyclical redundancy check (CRC) May 12, 2020 Issued
Array ( [id] => 17230740 [patent_doc_number] => 20210357297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => REAL TIME DATABASE BACKUP STATUS INDICATION AND RESTORE [patent_app_type] => utility [patent_app_number] => 15/931291 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931291 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/931291
Real time database backup status indication and restore May 12, 2020 Issued
Array ( [id] => 17729580 [patent_doc_number] => 11385967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Method for managing backup data by having space recycling operations on executed backup data blocks [patent_app_type] => utility [patent_app_number] => 15/930210 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930210
Method for managing backup data by having space recycling operations on executed backup data blocks May 11, 2020 Issued
Array ( [id] => 17136367 [patent_doc_number] => 11137920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-05 [patent_title] => Storing zones in a zone namespace on separate planes of a multi-plane memory device [patent_app_type] => utility [patent_app_number] => 15/929398 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929398 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929398
Storing zones in a zone namespace on separate planes of a multi-plane memory device Apr 29, 2020 Issued
Array ( [id] => 17136385 [patent_doc_number] => 11137938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-05 [patent_title] => Converting a multi-plane write operation into multiple single plane write operations performed in parallel on a multi-plane memory device [patent_app_type] => utility [patent_app_number] => 15/929399 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929399 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929399
Converting a multi-plane write operation into multiple single plane write operations performed in parallel on a multi-plane memory device Apr 29, 2020 Issued
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