Search

Tammara R. Peyton

Examiner (ID: 5819, Phone: (571)272-4157 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184, 2182, 2782
Total Applications
1681
Issued Applications
1471
Pending Applications
81
Abandoned Applications
147

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16371233 [patent_doc_number] => 10802994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => Caliberating a plurality of conductances of columns in memristor crossbar based computing [patent_app_type] => utility [patent_app_number] => 16/242660 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4689 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242660
Caliberating a plurality of conductances of columns in memristor crossbar based computing Jan 7, 2019 Issued
Array ( [id] => 16651854 [patent_doc_number] => 10929029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Memory controller and method for accessing memory modules and processing sub-modules [patent_app_type] => utility [patent_app_number] => 16/239542 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6745 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239542 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239542
Memory controller and method for accessing memory modules and processing sub-modules Jan 3, 2019 Issued
Array ( [id] => 16385283 [patent_doc_number] => 10810121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Data merge method for rewritable non-volatile memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 16/239535 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10088 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239535
Data merge method for rewritable non-volatile memory storage device and memory control circuit unit Jan 3, 2019 Issued
Array ( [id] => 16408860 [patent_doc_number] => 10817413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store data [patent_app_type] => utility [patent_app_number] => 16/216160 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216160
Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store data Dec 10, 2018 Issued
Array ( [id] => 16017915 [patent_doc_number] => 20200183801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => TRANSFERRING A WRITABLE DATA SET TO A CLOUD SERVICE [patent_app_type] => utility [patent_app_number] => 16/215971 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215971
Transferring a writable data set to a cloud service that is separate from the writable data set and terminate a snapshot after transfer Dec 10, 2018 Issued
Array ( [id] => 15757987 [patent_doc_number] => 10621107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => Translation lookaside buffer (TLB) clustering system for checking multiple memory address translation entries each mapping a viritual address offset [patent_app_type] => utility [patent_app_number] => 16/215840 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215840
Translation lookaside buffer (TLB) clustering system for checking multiple memory address translation entries each mapping a viritual address offset Dec 10, 2018 Issued
Array ( [id] => 14472563 [patent_doc_number] => 20190187925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => STORAGE SYSTEM, CONTROL DEVICE, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/216244 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216244
Deduplication storage system having garbage collection control method Dec 10, 2018 Issued
Array ( [id] => 14189147 [patent_doc_number] => 20190114279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => SCALABLE STORAGE BOX [patent_app_type] => utility [patent_app_number] => 16/214668 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214668
Scalable pooled NVMe storage box that comprises a PCIe switch further connected to one or more switches and switch ports Dec 9, 2018 Issued
Array ( [id] => 14473069 [patent_doc_number] => 20190188179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => Apparatus for Filtering Signals [patent_app_type] => utility [patent_app_number] => 16/204660 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204660
Apparatus for inter-integrated circuit (I2C) clock transmission channel wherein each filtering modules cooperates with the resistive circuit Nov 28, 2018 Issued
Array ( [id] => 14473035 [patent_doc_number] => 20190188162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => MEMORY MODULE AND OPERATION METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/203591 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203591
Delay circuit and write and read latency control circuit of memory, and signal delay method thereof Nov 27, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
Array ( [id] => 20539335 [patent_doc_number] => 12556417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 16/202079 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9796 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202079
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD Nov 26, 2018 Issued
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