Search

Tammara R. Peyton

Examiner (ID: 10365, Phone: (571)272-4157 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2182, 2782, 2184
Total Applications
1657
Issued Applications
1449
Pending Applications
87
Abandoned Applications
147

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18496253 [patent_doc_number] => 20230218822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => SENSOR MODEL SUPERVISOR FOR A CLOSED-LOOP INSULIN INFUSION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/118964 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 56691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18118964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/118964
Sensor model supervisor for temporary reductions in fluid delivery by a fluid delivery device Mar 7, 2023 Issued
Array ( [id] => 19283801 [patent_doc_number] => 20240220277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DEVICE CUSTOMIZATION WHILE REMAINING IN AN INTEGRAL OUTER PACKAGE [patent_app_type] => utility [patent_app_number] => 18/109401 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109401 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109401
DEVICE CUSTOMIZATION WHILE REMAINING IN AN INTEGRAL OUTER PACKAGE Feb 13, 2023 Pending
Array ( [id] => 19283801 [patent_doc_number] => 20240220277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DEVICE CUSTOMIZATION WHILE REMAINING IN AN INTEGRAL OUTER PACKAGE [patent_app_type] => utility [patent_app_number] => 18/109401 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109401 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109401
DEVICE CUSTOMIZATION WHILE REMAINING IN AN INTEGRAL OUTER PACKAGE Feb 13, 2023 Pending
Array ( [id] => 19334433 [patent_doc_number] => 20240248863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHOD AND APPARATUS FOR DATA TRANSFER BETWEEN ACCESSIBLE MEMORIES OF MULTIPLE PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM USING ONE MEMORY TO MEMORY TRANSFER OPERATION [patent_app_type] => utility [patent_app_number] => 18/099014 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099014
Data transfer between accessible memories of multiple processors incorporated in coarse-grained reconfigurable (CGR) architecture within heterogeneous processing system using one memory to memory transfer operation Jan 18, 2023 Issued
Array ( [id] => 19924850 [patent_doc_number] => 12299130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Method for secure, efficient startup of hyper-converged systems using hybrid centralization [patent_app_type] => utility [patent_app_number] => 18/098446 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1250 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098446
Method for secure, efficient startup of hyper-converged systems using hybrid centralization Jan 17, 2023 Issued
Array ( [id] => 19283955 [patent_doc_number] => 20240220431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SYSTEM, DEVICE AND/OR METHOD FOR SERVICING REDIRECTED MEMORY ACCESS REQUESTS USING DIRECT MEMORY ACCESS SCATTER AND/OR GATHER OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/149782 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149782
System, device and/or method for servicing redirected memory access requests using direct memory access scatter and/or gather operations Jan 3, 2023 Issued
Array ( [id] => 20117259 [patent_doc_number] => 12366962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => System method for improving read command process times in solid-state drives (SSD) by having processor split-up background writes based on determined command size [patent_app_type] => utility [patent_app_number] => 18/090358 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090358
System method for improving read command process times in solid-state drives (SSD) by having processor split-up background writes based on determined command size Dec 27, 2022 Issued
Array ( [id] => 19739770 [patent_doc_number] => 12216600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Neural network processing system for data moving method using direct memory access apparatus [patent_app_type] => utility [patent_app_number] => 18/089748 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 13084 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089748
Neural network processing system for data moving method using direct memory access apparatus Dec 27, 2022 Issued
Array ( [id] => 18471146 [patent_doc_number] => 20230205432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => DISAGGREGATED MEMORY SERVER [patent_app_type] => utility [patent_app_number] => 18/086488 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086488 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086488
Disaggregated memory server having chassis with a plurality of receptacles accessible configured to convey data with PCIe bus and plurality of memory banks Dec 20, 2022 Issued
Array ( [id] => 18296912 [patent_doc_number] => 20230106598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => Security Configurations in Page Table Entries for Execution Domains [patent_app_type] => utility [patent_app_number] => 18/064778 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064778
Security configurations in page table entries for execution domains Dec 11, 2022 Issued
Array ( [id] => 19718938 [patent_doc_number] => 12204475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Using a hardware sequencer in a direct memory access system of a system on a chip [patent_app_type] => utility [patent_app_number] => 18/064121 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 61 [patent_no_of_words] => 58557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064121
Using a hardware sequencer in a direct memory access system of a system on a chip Dec 8, 2022 Issued
Array ( [id] => 18264382 [patent_doc_number] => 20230085624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MODULAR SYSTEM (SWITCHBOARDS AND MID-PLANE) FOR SUPPORTING 50G OR 100G ETHERNET SPEEDS OF FPGA+SSD [patent_app_type] => utility [patent_app_number] => 18/074445 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18074445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/074445
MODULAR SYSTEM (SWITCHBOARDS AND MID-PLANE) FOR SUPPORTING 50G OR 100G ETHERNET SPEEDS OF FPGA+SSD Dec 1, 2022 Pending
Array ( [id] => 19756667 [patent_doc_number] => 20250045232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => ADAPTER FOR AN AUTOMATION FIELD DEVICE [patent_app_type] => utility [patent_app_number] => 18/713238 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18713238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/713238
ADAPTER FOR AN AUTOMATION FIELD DEVICE Nov 27, 2022 Pending
Array ( [id] => 19189530 [patent_doc_number] => 20240168443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => Customizing a Control System for Different Use Types [patent_app_type] => utility [patent_app_number] => 17/991509 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991509
Customizing a control system for different use types using a machine-trained model for generating and the modifying Nov 20, 2022 Issued
Array ( [id] => 19189530 [patent_doc_number] => 20240168443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => Customizing a Control System for Different Use Types [patent_app_type] => utility [patent_app_number] => 17/991509 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991509
Customizing a control system for different use types using a machine-trained model for generating and the modifying Nov 20, 2022 Issued
Array ( [id] => 18254903 [patent_doc_number] => 20230081942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => Automatically Deployed Information Technology (IT) System and Method [patent_app_type] => utility [patent_app_number] => 17/990264 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990264
Automatically deployed information technology (IT) system and method Nov 17, 2022 Issued
Array ( [id] => 18251944 [patent_doc_number] => 20230078983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => MEMORY DEVICE FOR COMPUTER [patent_app_type] => utility [patent_app_number] => 17/990169 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990169
Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from source Nov 17, 2022 Issued
Array ( [id] => 19167633 [patent_doc_number] => 11983542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Management of edge computing nodes in preboot execution environment (PxE) having unique media access control (MAC) address with targeted installation of edge node [patent_app_type] => utility [patent_app_number] => 18/056309 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 9589 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056309 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/056309
Management of edge computing nodes in preboot execution environment (PxE) having unique media access control (MAC) address with targeted installation of edge node Nov 16, 2022 Issued
Array ( [id] => 19053202 [patent_doc_number] => 20240095171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => INTERFACE FOR REMOTE MEMORY [patent_app_type] => utility [patent_app_number] => 18/054492 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054492 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054492
INTERFACE FOR REMOTE MEMORY Nov 9, 2022 Pending
Array ( [id] => 18912886 [patent_doc_number] => 11875871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Memory channels calibration during boot wherein channels are calibrated in parallel based on identifer [patent_app_type] => utility [patent_app_number] => 18/054056 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054056
Memory channels calibration during boot wherein channels are calibrated in parallel based on identifer Nov 8, 2022 Issued
Menu